Operations in RISC V - muneeb-mbytes/computerArchitectureCourse GitHub Wiki

Operations in RISC V

Operations are fundamental components of any instruction set architecture (ISA), including RISC-V, because they define the set of actions that the processor can perform

Arithmetic Operations

Instruction	Description	Example
add rd, rs1, rs2	Add contents of 2 registers.	add x5, x1, x2 - Sets x5 to the result of x1 + x2.
addi rd, rs1, imm	Add immediate value to the register.	addi x5, x1, 10 - Sets x5 to the result of x1 + 10.
sub rd, rs1, rs2	Subtract second register from first.	sub x5, x1, x2 - Sets x5 to the result of x1 - x2.
mul rd, rs1, rs2	Multiply contents of two registers (M extension).	mul x5, x1, x2 - Sets x5 to the result of x1 * x2.

Logical Operations

Instruction	Description	Example
and rd, rs1, rs2	Bitwise AND of two registers.	and x5, x1, x2 - Sets x5 to the result of x1 & x2.
or rd, rs1, rs2	Bitwise OR of two registers.	or x5, x1, x2 - Sets x5 to the result of x1 | x2.
xor rd, rs1, rs2	Bitwise XOR of two registers.	xor x5, x1, x2 - Sets x5 to the result of x1 ^ x2.
xori rd, rs1, -1	Bitwise XOR of register with immediate (bitwise NOT).	xori x5, x1, -1 - Sets x5 to the result of ~x1 (bitwise NOT of x1).

Shift Operations

Instruction	Description	Example
sll rd, rs1, rs2	Shift left logical by register.	sll x5, x1, x2 - Shifts x1 left by the number of positions specified in the least significant 5 bits of x2 and stores the result in x5.
slli rd, rs1, shamt	Shift left logical by immediate.	slli x5, x1, 3 - Shifts x1 left by 3 positions and stores the result in x5.
srl rd, rs1, rs2	Shift right logical by register.	srl x5, x1, x2 - Shifts x1 right by the number of positions specified in the least significant 5 bits of x2 and stores the result in x5.
srli rd, rs1, shamt	Shift right logical by immediate.	srli x5, x1, 3 - Shifts x1 right by 3 positions and stores the result in x5.
sra rd, rs1, rs2	Shift right arithmetic by register.	sra x5, x1, x2 - Shifts x1 right arithmetically by the number of positions specified in the least significant 5 bits of x2 and stores the result in x5.
srai rd, rs1, shamt	Shift right arithmetic by immediate.	srai x5, x1, 3 - Shifts x1 right arithmetically by 3 positions and stores the result in x5.

Comparison Operations

Instruction	Description	Example
slt rd, rs1, rs2	Set Less Than.	slt x5, x1, x2 - Sets x5 to 1 if x1 is less than x2, otherwise sets x5 to 0.
slti rd, rs1, imm	Set Less Than Immediate.	slti x5, x1, 10 - Sets x5 to 1 if x1 is less than 10, otherwise sets x5 to 0.
sltu rd, rs1, rs2	Set Less Than Unsigned.	sltu x5, x1, x2 - Sets x5 to 1 if x1 is less than x2 (unsigned), otherwise sets x5 to 0.
sltiu rd, rs1, imm	Set Less Than Unsigned Immediate.	sltiu x5, x1, 10 - Sets x5 to 1 if x1 is less than 10 (unsigned), otherwise sets x5 to 0.

Load and Store Operations

Instruction	Description	Example
lw rd, offset(rs1)	Load Word.	lw x5, 0(x1) - Loads the 32-bit value from the memory address x1 + 0 into x5.
sw rs2, offset(rs1)	Store Word.	sw x5, 0(x1) - Stores the 32-bit value from x5 into the memory address x1 + 0.

Branch Operations

Instruction	Description	Example
beq rs1, rs2, offset	Branch if Equal.	beq x1, x2, label - Branches to the address label if x1 is equal to x2.
bne rs1, rs2, offset	Branch if Not Equal.	bne x1, x2, label - Branches to the address label if x1 is not equal to x2.
blt rs1, rs2, offset	Branch if Less Than.	blt x1, x2, label - Branches to the address label if x1 is less than x2.
bge rs1, rs2, offset	Branch if Greater Than or Equal.	bge x1, x2, label - Branches to the address label if x1 is greater than or equal to x2.