Memory access with 2 level Page Table

The segment register contains the address of starting point of the segment table and this tells which particular entry you want in that table. By adding with the appropriate weight age will leads you to the location of segment table which you want to refer to. We are assuming that segment table would be in the physical memory, it is comparatively much smaller.

So when you make an access to this entry it will either tell you that the corresponding page table is not present. That is a page fault or it will tell you where it is present. So now in case of a hit this address will be the starting address of the relevant page table and to that we can add the page number again with appropriate weight age to get the exact location of the page table entry.

Let's imagine we have some i th page table. In this case, We could identify a page fault or succeed. If it's successful then we will obtain the actual page number or byte of the term which we are looking for.

Memory access with paged Page Table

Here we have 2 fields in the virtual address. (u) stands for user's virtual space , (s) stands for system's virtual space, (p) is for physical space.

The starting point is virtual address which is in user’s virtual space and it consists of page part, page number and the byte number. The base address will be available in the register User Page Table (UPT). It is not a physical address. Since it is a virtual address in system virtual space. So the starting address plus page offset will give another virtual address in the system space which will again look up on page part and byte part.

The page number indicates that it is a page in the system's virtual space. The base of the System Page Table (SPT) is a physical address. A physical address with a memory access will be obtained by adding the physical address present in the SPT and page number offset. This location will indicate whether there is a page fault or provide a physical page number. The obtained physical page number with the byte number will give the address of user's page table.

We shall obtain a physical page number or a page fault from the user's page table. This physical page number and byte number can be used to obtain another physical address, which is a translated portion of the virtual address.

Translation Lookaside Buffer (TLB)

The page table is large and is usually located in physical memory. If a processor executes load or store instruction, the system requires two access of the main memory :

• one for translation (page table read)
• another to access data (after translation) These accesses eventually degrade the memory performance in half, unless we get clever way to access the memory.

Translation Lookaside Buffer (TLB) is a small cache of most recent translations, and reduces the number of memory accesses for most loads\stores from 2 to 1.

The above figure shows Paging Hardware with TLB

The CPU only looks at the virtual address which consists of VPN (Virtual Page Number) and PO (Page Offset). If the corresponding PPN (Physical Page Number) is already in Translation look-aside buffers, the system will get TLB hit. VPN is directly translated into PPN using TLB located within the CPU. In this case, only one memory access is required.

If the page number is not in the TLB (TLB miss), the system searches the page table which is located in the main memory. After getting PPN in the main memory, it can translate VPN into PPN, and then access the data located in the memory. In this case, two memory accesses are required.

When we run multiple processes (programs) at once, each process has its own page table. Each process can use entire virtual address space. A process can only access physical pages mapped in its own page table.

Overall operation

There is a page table (PT), cache, and TLB in the overall operation.

First thing which we wanted to do is a TLB access. TLB access is basically a shortcut to do in page table access.

• If the TLB access is successful, it will proceed to cache.

  • There will be another hit or miss in the cache level following a successful TLB access. If it is successful, we will retrieve the data directly from the cache and send it to the CPU. so there is absolutely no access to physical memory.
  • If there is a miss at the cache access, then it will access the physical memory.

• If the TLB access is a failure, it will proceed to page table access.

  • There will be another hit or miss in the page table. If it is successful, then will get a physical address to make an access to cache.
  • If there is a miss at the page table, then will get a page fault.