Instruction Set Architecture (ISA)

• An Instruction Set Architecture (ISA) defines the interface between software and hardware. Software is converted to machine instructions using software (compiler/interpreter). Then the instructions are executed using hardware.
• A compiler translates high-level source code (e.g., C++, C) to the ISA for a target processor, The processor directly executes ISA instructions
• In simple words an Instruction Set Architecture (ISA) defines the communication rules between the hardware and software of the computer. The ISA is a design principle and is not stored in a computer’s memory.
• Some things an ISA defines:
  1. How binary instructions are formatted
  2. What instructions are available to be processed on a specific hardware setup
  3. How computer memory is accessed

Complex Instruction Set Computers (CISC)

• CISC (Complex Instruction Set Computer) is an ISA design practice that focuses on multi-step instructions and complex, power-consuming hardware. These designs primarily focus on hardware components and binary instruction complexity.
• CISC Instructions Attributes:
  1. Single instructions take more than one CPU cycle to complete
  2. Instruction length varies based on the instruction type
  3. Hardware must be designed to accept more complicated instructions
• A single instruction can do many things, Instructions are often variable-size to minimize RAM usage
• Example intel X86

Reduced Instruction Set Computers (RISC)

• RISC (Reduced Instruction Set Computer) is an ISA design practice of ISAs that focuses on simple, quickly executed instructions to improve efficiency and reduce power consumption. These designs primarily focus on simple hardware components and reducing binary instruction complexity. Processing components are typically not interchangeable with CISC-designed systems.
• General RISC Instructions Attributes:
  1. Single instructions take only one CPU cycle to complete
  2. Instruction lengths are fixed, regardless of the instruction type
  3. Reduced complexity of hardware leads to less power consumption at the expense of overall processing times.
• RISC ISAs usually have fixed-sized instructions and a load/store architecture
• Example MISP and ARM

Analogy

consider a word fallible which means "able to make mistake", here fallible can considered as a CISC type instruction i.e. a Single word conveys a complex meaning. While "able to make mistake" is RISC type architecture which requires 4 words to convey same information as fallible.

Lets take an example of multiplication operation with two methods.

Method 1: multiplicand = 2 multiplier = 5

(multiplicand is the number or quantity we are multiplying, and multiplier is the number we multiply by)

multiplicand X multiplier = Product

2 X 5 = 10

Method 2: By repeated addition of multiplicand by number of times of multiplier.

2 + 2 + 2 + 2 + 2 = 10

Method 1 is a complex single instruction, whereas Method 2 is a simple addition multiple times. If CISC uses one complex instruction to perform an operation but RISC uses multiple simple instructions to perform the same operation. The possibility of making mistakes is high in RISC when compared to CISC.

MIPS (Microprocessor without Interlocked Pipelined Stages)

• MIPS belongs to the family of RISC instruction set architecture
• It is a 32-bit architecture. Registers are 32-bits wide, All instruction types are 32-bits long.
• It is a load/store type architecture.
  • Load: Read a value from a memory address into a register
  • Store: Write a value from a register into a memory location
  • So, to manipulate memory values, a MIPS program must
  • Load the memory values into registers
  • Use register-manipulating instructions on the values
  • Store those values in memory

RISC-V Architecture:

• RISC-V is a Reduced Instruction Set Computing (RISC) architecture, emphasizing simplicity and efficiency in instruction design.
• RISC-V has a variable-width instruction set, allowing instructions of different lengths. This flexibility simplifies instruction decoding. 32/64/128-bit
• RISC-V supports 32, 64, and 128-bit data widths. The width determines the size of registers and memory addresses, offering scalability for various applications.
• RISC-V features a set of general-purpose registers. The number and size of registers are defined by the standard, providing consistency across implementations.
• Similar to MIPS, RISC-V follows a load/store architecture. To manipulate memory, values are loaded into registers, operated on, and then stored back in memory.
• RISC-V maintains simplicity in its instruction set, with a reduced number of instructions compared to complex architectures like x86.
• RISC-V is an open standard, meaning that anyone can implement processors based on the architecture without paying licensing fees.

x86 architecture:

• x86 is a complex instruction set computing (CISC) architecture, offering a wide range of instructions that can perform complex operations.
• It started as a 16-bit architecture and evolved into 32-bit and 64-bit modes. Registers and memory addresses can be 16, 32, or 64 bits wide, depending on the mode.
• x86 has general-purpose registers that store data and addresses. The number and size of registers depend on the operating mode.
• Unlike MIPS, x86 isn't strictly load/store. It supports various memory-to-memory and register-to-register operations, reducing the need for explicit load and store instructions.
• x86 instructions can vary in length from 1 to 15 bytes, unlike the fixed-length 32-bit instructions in MIPS.
• x86 maintains backward compatibility, allowing modern processors to run software developed for older x86 processors.

Motorola 68000:

• The Motorola 68000, commonly known as the "68000" or "68k," is a 16/32-bit microprocessor that belongs to the family of Complex Instruction Set Computing (CISC) architectures.It was developed and first released by Motorola in the late 1970s, and it gained popularity as a powerful and versatile microprocessor used in various computing systems.
• The 68000 has a rich and extensive instruction set that includes a variety of addressing modes and instructions for performing arithmetic, logical, and control operations.The instructions are relatively complex compared to the simpler instructions found in RISC architectures.
• The 68000 is designed to handle multiple data types, including 8-bit, 16-bit, and 32-bit integers. It supports both signed and unsigned arithmetic operations.
• The 68000 architecture includes a set of general-purpose registers, including data registers and address registers. These registers are used for data manipulation and addressing calculations.
• The 68000 has a sophisticated memory management system that supports virtual memory and allows the processor to address large amounts of memory.
• The 68000 typically uses a 16-bit external data bus and a 24-bit external address bus, providing access to a large address space. Later versions, such as the 68020, expanded the data bus to 32 bits.
• The Motorola 68000 found widespread use in various applications, including personal computers, workstations, embedded systems, and arcade machines.It was the processor used in early Apple Macintosh computers and several generations of Atari and Commodore computers.
• Despite being an older architecture, the Motorola 68000 still holds a place in computing history, and its design influenced subsequent generations of processors. Some embedded systems and legacy applications may still use 68000-based processors.
• The 68000 architecture evolved with successors such as the 68010, 68020, 68030, and so on, each introducing enhancements and improvements.