Control Hazard - muneeb-mbytes/computerArchitectureCourse GitHub Wiki

CONTROL HAZARDS

Control hazards refer to delays in instruction execution caused by the pipeline structure of a processor encountering branches or other control flow instructions whose outcomes are not immediately known. These hazards occur because the decision on which instruction to execute next depends on the outcome of the control instruction, which is typically resolved in a later pipeline stage. Control hazards can lead to pipeline stalls or bubbles where the processor waits for the control instruction's outcome before proceeding with the correct sequence of instructions.

Let's look at an example from the Branch If Equal instruction.

The instruction "beq" means to compare the values of two registers $t1 and $t2; if the values in both registers are equal, it jumps to the instruction with the label L. If not, then the next instruction is executed.

Considering the false condition in the given instruction:

There will be parallel execution, thus if the register contents are not equal, the next instruction is performed, and there is no risk of a flush, resulting in no control hazards.

Now Considering the true Condition for the above case.

Even here execution happens parallelly, so if the register values are equal then it jumps to the instruction which has a label L. But the instructions next to the beq instructions have started the execution, and they must be flushed out because the actual execution to be performed is an instruction labelled L. This, in turn, produces a hazard known as the control hazard.

Solution of control hazard

Usually when we take any conditional statements like if-else statements, we give more priority to the if condition than the else condition, that is we would want the if condition to be true than with the else condition.

Similarly in this case we need to code the branch condition in such a way that the else condition is preferred to be true than the if condition so that we give more priority to the else condition than if condition.

Hence in the first case, the next instruction will be executed but not the instruction with label L. So in order to overcome this hazard, we need to prioritize the else condition.