Constant Value in Hardware - muneeb-mbytes/computerArchitectureCourse GitHub Wiki

What happens when a constant is declared ?

Ever wondered what is the hardware implementation for the constant values in verilog/systemVerilog

    module top(clk,d);
    input clk;
    output reg d;
    parameter reg a = 0;
    always@(posedge clk)
    begin
      d<=a;
    end
    endmodule

Here a is hardwired to zero. In terms of hardware a is grounded.