MIPS Instruction Formats

Opcode

It specifies the operation to be performed

MIPS Register Set

MIPS Register Set consists of 32 general purpose registers($0-$31). The width of each register is 32 bits

Data Access and Storage: Registers coupled to the processor allow faster access to data because fetching data from main memory is slower. Registers are used as temporary storage elements that store data during operation performed by CPU.

Efficient Communication: Fetching repetitive code from the main is time consuming and less efficient. The register set can be used to store the temporary code and allow faster and efficient communication between the memory and CPU.

CPU Control and Status: The register set includes special purpose registers such as program counter (PC). Thess are used to store data which controls the process and aids the CPU. The PC for example is used to store the address of next instruction to be executed.

Optimization and pipelining: MIPS architecture supports instruction pipelining which is dividing an instruction into many stages. The data flow during these stages are effectively managed by these registers. The design of these registers helps complier to automatically create an optimised code and enhance the overall performance.

Why MIPS has 32 registers?

In MIPS instructions, three registers (two sources and one destination) are specified within the 32-bit instruction length. MIPS architecture allocates 5 bits per register, allowing a maximum of 32 registers (2^5=32). If 32 registers require 5 bits, it consumes 15 bits of the 32-bit MIPS instruction (when using 3 registers). Opting for 6 bits per register would allow up to 64 registers, but it would impact space for other constants or opcodes in instructions

Why MIPS instructions are 32-bit wide?

• Speed of operation: Smaller registers were faster and easier to access at the time of MIPS development

*** Instruction Length:** The 32-bit register size aligns with MIPS instruction length, limiting the number of registers that can be accessed in a single instruction.

• Efficient Data Access: The 32-bit register size facilitates efficient and fast access to registers, contributing to overall processor performance.

• Compatibility and Design Simplicity: The consistent 32-bit register size across different MIPS architecture versions contributes to compatibility and design simplicity.

1. I format:

Have 2 registers and a constant value immediately present in the instruction.

• opcode (6 bits)
• rs: source register (5 bits)
• rt: destination register (5 bits)
• immediate value (16 bits)

Range of the n bit integer: -2^(n-1) to 2^(n-1)-1 For 16 bit signed integer range is: -2^(15) to 2^(15)-1 -322768 to 32767

Case (1) Adding the content of register with constant value and put into a temporary register: Eg: addi $21,$22,50 Opcode=8 rs=s3(register contain operand) rt=t0(target register ) immediate=50 similarly: opcode=addi; rs=s3=10 Immediate =124 rt=t2=134

Case (2) For load operation : Lw $10

Case (3) To store the values Sw $t0 4($s1)

2. J format:

● Have an address (part of one, actually) in the instruction.

The J format is used for jump or branch instructions, which involve changing the program counter to jump to a different instruction Pointer points where to go next The address in J format is larger than the I-format The address is 26 bits Range is -2(^25) to 2^(25)-1

Steps to represent the address in J format and the reconstruction:

Consider the example : J 400

Reason behind reducing the last two binary digits :

Since the last two bits are always 00, they do not need to be stored in the instruction. This reduces the memory space from 32 bits to 30 bits.

Example 2: J 2000

To represent an address in J format, follow these steps: Convert the address to an 8-digit hex value.

Drop the first hex digit. Convert to binary. Drop the last 2 binary digits. For address 2000: Convert to hex: 0000_07D0 Drop the first digit: 00007D0 Convert to binary: 0000_0000_0000_0000_0111_1101_0000 Drop the last 2 bits: 00000000000000000111110100 This results in 26 bits: 00000000000000000111110100 = 500 in decimal. Alternatively, divide the address by 4: 2000 / 4 = 500. To form the 32-bit jump target: Append two zeros to get a 28-bit address: 500>>2=4000 Add the first 4 bits of the PC to the beginning Or simply multiply by 4. J format supports 2^(26+2) = 268435456 = 256MB range of addresses. 26 bit signed integer value should fall within range of: -2^(25) to 2^(25)-1 = -33554432 to +33554431.

3. R – format

• The R format instruction is used when the input values to the ALU comes fromtwo registers.
• 3 register operands are used (2 source registers rs1,rs2 , 1 destination register rd).

• rs: 1st register operand (register source) (5 bits).
• rt: 2nd register operand (5 bits).
• rd: register destination (5 bits).
• shamt: shift amount (0 when not applicable) (5 bits).
• funct: function code (identifies the specific R-format instruction) (6 bits).

Example:

• Registers(16,17,18)=Registers($s0,$s1,$s2).

RISC-V Instruction Sets

• RISC- V is an open source instruction set architecture used to develop custom processors for a variety of applications.
• RISC-V has 32, 64 and 128 bit variants. It has 31 general purpose registers (x1 –x31) and two special registers x0 and pc in its base variant.

Levels Of Representation:

Below diagram represents transforming Higher-Level Language Programs into Machine Language, includes stages of: • Compilation, assembly, machine interpretation. • Hardware architecture description and implementation.

REGISTERS IN RISC-V

There are 32 general purpose registers which are 32 bits wide.

Base Instruction Format

In RISC-V architecture base instruction sets are differentiated into several instruction formats. These formats dictate how the fields of an instruction are arranged in a 32-bit word. These formats are of 4 types:

1. R-type:

• R type refers to register type, utilized in arithmetic and logical operations.
• It includes a 7-bit opcode that determines the specific operation.
• The destination register (rd) is a 5-bit field that indicates the result location.
• Funct3 is a 3-bit field providing additional information.
• This type involves 3 register operands: 2 source registers (rs1 and rs2) indicating the input sources.
• Funct7 is a 7-bit field offering further details. Example: ADD rd, rs1, rs2 This instruction adds the contents of rs1 and rs2 registers and stores the result in the rd register.

2. I-type:

• I type, or immediate type, is used for operations involving immediate values.
• It has a 7-bit opcode to define the operation.
• The 5-bit rd field specifies the destination register.
• Funct3 is a 3-bit field that gives extra operation details.
• Rs1 is a 5-bit field that identifies the source register.
• The imm[11:0] field is 12 bits and holds the immediate value. Example: ADDI rd, rs1, imm12 This instruction adds the sign-extended immediate value (imm12) to the contents of register rs1 and stores the result in register rd.

3. S-type:

• S in S-type stands for Store instructions, specifically used for storing data.
• The opcode, stored in a 7-bit field, defines the operation.
• The immediate (imm) field is split into two parts: imm[11:5] (bits 31 to 25) and imm[4:0] (bits 11 to 7).
• Funct3 is a 3-bit field that holds additional information.
• Rs1 and Rs2 are 5-bit fields, with Rs1 being the base address register and Rs2 being the source register. Example: SW X14, 8(X2) This instruction stores the contents of register X14 into memory at the address formed by adding the immediate offset value 8 to the contents of register X2. It belongs to the S-Type format, where 8 is the immediate offset.

4. U-type:

• U-type stands for Upper Immediate instruction set, used for instructions with a 20-bit immediate value.
• The opcode, in a 7-bit field, specifies the type of operation.
• Rd is a 5-bit field for the destination register.
• Imm is a 20-bit field for the immediate value.
• U-type instructions are used when immediate values are larger than 12 bits and I-type can't accommodate them. Example: LUI rd, imm20.This instruction loads the 20-bit immediate value (imm20) into the upper 20 bits of register rd, filling the lower 12 bits with zeros.