Additional information on RARS simulator - muneeb-mbytes/computerArchitectureCourse GitHub Wiki

Instruction in RISC V : (I format)

                                                      addi t1, t2, 5    

Output: 0x00538313

Hexadecimal: 0x00538313

Binary: 0000_0000_0101_0011_1000_0011_0001_0011

We know, I format in RISC V

Hexadecimal: 0x00538313

Binary: 000000000101_00111_000_00110_0010011

i format : immediate-value_rs1_funct3_rd_opcode

Opcode (7 bits): The opcode for the "addi" operation in RISC-V is 0010011. In binary, this is represented as 0010011.

rd (5 bits): For rd = t1 (x6), in binary, this is represented as 00110.

Funct3 (3 bits): For the "addi" operation, the funct3 field is 000. In binary, this is represented as 000.

rs1 (5 bits): For rs1 = t2 (x7), in binary, this is represented as 00111.

Immediate value (12 bits): The immediate value 5 in binary is represented as 000000000101.

Combining all these components into a 32-bit representation:

Opcode: 0010011

rd: 00110

Funct3: 000

rs1: 00111

Immediate value: 000000000101

Here, 0x00400000 is the memory address where the machine code of an instruction is stored.

In computer architecture, the program counter (PC) is a register that keeps track of the memory address of the next instruction to be executed

So PC is pointing to 0x00400004