format of "beq" instruction

The branch instruction has this format opcode which is in the I - format for load store, rs and rt are the two registers which will be compared and this number would be added as word offset to PC and it will be PC plus 4 to which will be add because that part we want to retain as common for all the instructions.

Instead of sending PC plus 4 back directly to PC it can have more options and the options would be that this with something added to it.

adding "beq"

For branch instruction the upper part need to be modified this and will use ALU for equality test. The comparison will be done and ALU will produce a bit which will indicate whether the two inputs are equal or unequal.

First of all this is a multiplexer which is making a choice; either to take PC plus 4 or to take output of the adder which is adding something to PC plus 4.

Here a 16-bit constant which has been sign extended but it is also been shifted has been added. The s2 using to shift this number by 2 bits to the left which is effectively multiplying by 4 and getting a byte number from word number.

It has been the correct offset coming here which gets added to PC plus 4 and is available to this multiplexer. Now the multiplexer has to look at which instruction it is;

if it is not branch instruction it will simply allow this to go through if it is branch instructions then it looks at the result of comparison in the ALU and accordingly a 0 or 1 will be chosen here.

Adding "j" instruction

Recall that the jump instruction j has the following format. This gives 26 bits to say where we are jumping to.

• We have 6 bits for the opcode.
• We have 26 bits for the target address.

We do not have enough space in the instruction to specify a full target address. Since it is not a full 32-bit address we need to retain some bits of PC as it is. Branching solves this problem by specifying an offset in words.

• Take the 26-bit target address field of the instruction, left-shift by two to get 28 (instructions are word-aligned).
• Pick 4 bits from PC+4 (namely, bits 28-31).
• concatenate 4 bits and 28 bits together to form a jump address which is a 32-bit value and this will go back to the program counters.