Welcome to the computerArchitectureCourse wiki!

Sr.no	TOPICS	Videos Referred	Page Numbers Referred
1	History of Computers	Lecture 2	134 to 152
2	Introduction to Computer Architecture	Lecture 1	39, 52, 59, 61, 67
3	Instruction Set Architecture 1	Lecture 3	26-27, 320-323
4	Instruction Set Architecture 2	Lecture 4	26, 27, 167, 169, 179, 320, 321, 322 & 323
5	Instruction Set Architecture 3 & Recursive Programs	Lecture 5 & Lecture 6	Lecture 5: 218-226 & Lecture 6: 227-228, 231
6	Architecture Space	Lecture 7	206, 210, 221, 232, 239, 246
7	Architecture Examples	Lecture 8	350-357
8	Processor Design-1	Lecture 17	476-487
9	Processor Design-2	Lecture 18	488 -515
10	Processor Design-3	Lecture 19	510-516
11	Processor Design-4	Lecture 20	522-525
12	Processor Design-5	Lecture 21	563-569
13	Processor Design-6	Lecture 22	1393-1438
14	Processor Design-7	Lecture 23	602-611
15	Pipelined Processor-1	Lecture 24	518-526
16	Pipelined Processor-2,3,4	Lecture 25 Lecture 26 & Lecture 27	526-536
17	Memory Hierarchy-1	Lecture 28	739-740
18	Memory Hierarchy-2	Lecture 29	745-749
19	Memory Hierarchy-3	Lecture 30	1328
20	Memory Hierarchy-4	Lecture 31	819 - 839
21	Memory Hierarchy-5	Lecture 32	850

Additional Concepts

Sr.no	TOPICS
1	Difference between import and `include
2	Difference between class and Structure
3	Pseudo Randomization
4	Seed Number
5	Constant Values in Hardware
6	HTTP vs SSH
7	Why Write Strobe and No Read Strobe in AXI
8	Power Down Techniques

TEAM PROJECT : Designing a Simple RISCv Processor

TEAM	Github code	wikipage
1	https://github.com/rakshitharnayak/RISC--V-Processor	https://github.com/rakshitharnayak/RISC--V-Processor/wiki
2	https://github.com/dhanasekarp03/RISCV	https://github.com/dhanasekarp03/RISCV/wiki
3	Github code link	Github wiki link

Batch 9 CA Summaries

Sr.no	TOPICS
1	Session 2
2	Session 3
3	Session 4
4	Session 5
5	Session 6
7	Session 7
8	Session 8