4.Transfers - muneeb-mbytes/axi4_avip GitHub Wiki

Write and Read Operations

Here are some steps on how a write transaction can happen and what are the possible states or values for the signals involved in the write channel for successful writing of data-

Single data transfer

Write

  • Master sends AWADDR(address on which write to be performed) with AWVALID to be high mentioning it's a valid address.
  • Slave asserts AWREADY informing it is ready to accept the operation. Now that the handshake is done it is ready for data transfer.

Data transfer

  • In the next clock cycle after AWREADY is high or after some clock cycles slave asserts WREADY indicating it is ready.
  • Master transfers data in WDATA bus with WVALID high.
  • Master also asserts WLAST to be high as it is single data transfer.
  • Slave responds with BRESP with BVALID high whenever the master asserts BREADY to be high indicating the success or failure of write transaction.

Multiple data transfers with a burst

  • While the handshaking in progress, starting address of the burst AWADDR, burst type AWBURST, burst length AWLEN, burst size AWSIZE are sent to the slave.
  • In the next step, master sends WDATA in the number of cycles as the number of data transfers mentioned before with WVALID high.
  • Also, it asserts WLAST for the last data transfer.
  • Slave responds later after all the data transfers are complete.

Note:
->BRESP is sent from slave after the whole burst transaction is complete and not for each data transfer.
->READY signals can be sent without or with respect to the VALID signals of the source.

READ

  • Similar to write operation the read starts by sending a address along with valid and ready in address read channel.
  • When it comes to read data channel, the ready signal will be from the master whereas valid along with data and response are sent by the slave.

Transaction Ordering Rules

  • Write data must follow same order as the addresses that are transferred with AWADDR signal.
  • Transactions with different IDs can complete in any order.
  • A master can have multiple outstanding transactions with the same ID, but they must be performed in order and complete in order.
  • Masters have to put W channel data in the same order as AW channel's data. Mixing orders between multiple transactions on AW and W channels is not allowed. In AXI3 the order of write data were altered by giving its specific IDs and based on the ID specified with the write data the slave was able to identify its write address.
  • Read data with different IDs have no restrictions on ordering. So slave can send in any order.
  • The read data that having different IDs can be interleaved in any order.
  • The read data with same IDs should be transferred in the requested order.

Unaligned Transfers

AXI supports unaligned transfers. For any burst that is made up of data transfers wider than one byte, the first bytes accessed might be unaligned with the natural address boundary. For example, a 32-bit data packet that starts at a byte address of 0x1002 is not aligned with the natural 32-bit address boundary.

A master can:

  • use the low-order address lines to signal an unaligned start address.
  • provide an aligned address and use the byte lane strobes to signal the unaligned start address.
  • The information on the low-order address lines must be consistent with the information on the byte lane strobes.
  • The slave is not required to take special action based on any alignment information from the master.
  • The AXI protocol supports transactions with an unaligned start address that only affects the first transfer in a transaction. After the first transfer in a transaction, all other transfers are aligned.
  • The AXI protocol also supports unaligned transfers using the strobe signals. An unaligned transfer is where the AxADDR values do not have to be aligned to the width of the transaction. For example, a 32-bit data packet that starts at a byte address of 0x1002 is not aligned to the natural 32-bit address boundary because 0x1002 is not exactly divisible by 0x20.

The following example shows a 5-beat 32-bit transfer starting at an unaligned address of 0x01:

ssssss

Fig.1 unaligned transfer with 32-bit

  • If the transaction were aligned to a start address of 0x00, the result would be a five-beat burst with a width of four bytes giving a maximum data transfer of 20 bytes.
  • However, we have an unaligned start address of 0x1. This reduces the total data volume of the transfer, but it does not mean a final unaligned transfer to complete the burst and make up the volume. In this example, the first transfer starts at address 0x01 and contains three bytes. All the following transfers in the burst are aligned with the bus width and are composed of four bytes each.

The following example shows a five-beat 16-bit-sized transaction starting at address 0x03:

image

Fig.2 unaligned transfer with 16-bit

  • If the transaction were aligned to a start address of 0x00, the result would be a five-beat burst with a width of two bytes giving a maximum data transfer of 10 bytes. In this example, the first transfer starts at an unaligned address of 0x03 and contains one byte. All the following transfers in the burst are aligned with the bus width and are composed of two bytes each. The AXI protocol does not require the slave to take special action based on any alignment information from the master.

  • From the example and the content, we could say that the main purpose of the unaligned transfer is that here we just fill data in the required locations using the Strobe signal so that no allocation is wasted. as we mentioned it will be as usual from the next byte.

Read and write channel ordering rules

Generally AXI had 5 separate channels in which 3 channels are used for write and 2 channels are used for read operations. As there are different channels for write and read so Read and write channels have no ordering rules in relation to each other. As AXI supports parallelism so read and write operations can be performed anytime it means both read and write operations can be performed at same time .so if we want continuous write read operation the read signal does not wait for any write response channel. When master wants to perform specific order of write read operations we have to make sure that this transaction should be completed before issuing the new transaction. But in a transaction for every read and write operations all the channels should satisfy the handshake mechanism by making the both valid and ready signal high. As AXI has separate write and read channels so even we can perform both the write and read operations on same address location but we cannot determine whether the write operation takes first or read takes place first.
when the master requires a specific ordering for a write read-write transaction sequence from an address the sequence of operations is as follows:

  1. The master starts the first write transaction.
  2. The master ensures that the slave has completed the write transaction by waiting for the signal on the Write Response channel.
  3. The master starts the read transaction.
  4. The master waits for the final response on the Read Data channel.
  5. The master starts the second transaction of write operation