3.Burst types - muneeb-mbytes/axi4_avip GitHub Wiki

The burst type is specified by:

  • ARBURST[1:0], for read transfers

  • AWBURST[1:0], for write transfers.

The below table shows the AxBURST signal encoding. Here AxBURSTindicates ARBURST or AWBURST.

AxBURST[1:0] Burst type
0b00 FIXED
0b01 INCR
0b10 WRAP

Burst type

The AXI protocol defines three burst types:

FIXED

In a fixed burst:

  • The address is the same for every transfer in the burst.

  • The byte lanes that are valid are constant for all beats in the burst. However, within those byte lanes, the actual bytes that have WSTRB asserted can differ for each beat in the burst.

  • This burst type is used for repeated accesses to the same location such as when loading or emptying a FIFO.

fixed burst

For e.g. let us assume a scenario where start_addr = 0, write data bus width (wdb) = 4B, bus length = 3 (that means 3 +1 = 4 beats). Starting address will be considered as '0'. Since wdb is of 4B and size is 4B and bus length is 4 beats that means, there are 4 transactions (bus length) and each transaction consists of 4B. So after 3rd location since it is fixed it will start again with '0' location for next transaction. FIFO will target the starting address at that particular location.

INCR

Incrementing. In an incrementing burst, the address for each transfer in the burst is an increment of the address for the previous transfer. The increment value depends on the size of the transfer. For example, the address for each transfer in a burst with a size of four bytes is the previous address plus four.

This burst type is used for accesses to normal sequential memory.

Example

 Given start_addr = 0X00 , awsize = 2, awlen = 3 

Now,
size of transaction (burst size) = 2 ^ awsize 
                                 = 2 ^ 2 
                                 = 4
burst length = awlen + 1
             = 3 + 1 
             = 4

total no of transfers   = burst length X size of transaction
                          = 4 X 4
                          = 16

Next Address = Previous address + burst size

The address will be incremented as : 0X00, 0X04, 0X08, 0X12

WRAP

A wrapping burst is similar to an incrementing burst, except that the address wraps around to a lower address if an upper address limit is reached.

The following restrictions apply to wrapping bursts:

  • the start address must be aligned to the size of each transfer

  • the length of the burst must be 2, 4, 8, or 16 transfers.

Calculation of a wrapping boundary is:

  1. Lower wrap boundary= INT(start_addr / (burst length X size of transaction)) X (burst length X size of transaction)

  2. Upper wrap boundary= Lower wrap boundary + total transaction size.

    [here total transaction size = (burst length * burst size)]

Then the address wraps round to the wrap boundary.

Example

 Given start_addr = 0X40 , awsize = 2, awlen = 3 

Now,
size of transaction (burst size) = 2 ^ awsize 
                                 = 2 ^ 2 
                                 = 4
burst length = awlen + 1
             = 3 + 1 
             = 4

total no of transfers   = burst length X size of transaction
                          = 4 X 4
                          = 16

Lower boundary     = INT(start_addr / (burst length X size of transaction)) X (burst length X size of transaction)
                   = INT(64 / 16) X 16  [0X40 in decimal is 64]
                   = 4 X 16
                   = 64 
                   = 0X40 [in hex]

Upper boundary   = Lower boundary + total no of transactions
                   = 0X40 + 16 [0X10 in hex]
                   = 0X50

Next Address = Previous address + burst size

The address will be incremented as : 0X40, 0X44, 0X48, 0X40 (0X52 should be next, but this occurs at upper boundary address, so next 
                                         address will be wrapping to lower boundary 0X40)