AMBA AXI PROTOCOL

Overview:

AMBA (Advanced Microcontroller Bus Architecture) is open standard for communication and management of the functional blocks in SoC, provide different on chip communication protocols like CHI (Coherence Hub Interface), AXI (Advanced eXtensible Interface), ACE (Advanced Coherency Extension), AHB ( Advanced High Performance Bus), APB (Advanced Peripheral Bus) developed by ARM (Advanced RISC Machine ) . Flexibility of AMBA protocols is IP reuse for different SoC designs with different area, power and performance requirements.

As the AMBA protocols are widely used open standards which ensures compatibility between IPs of different suppliers for the SoC , with compatibility it enables low friction integration and reuse of IP which catalyse the faster time to market. The AMBA AXI protocol specification is defined to implement a high frequency, high bandwidth interface across a wide variety of applications in embedded, automotive and cellphones. It does not require complex bridge implementation for different peripheral devices. The AXI protocol includes some new features which extend previous versions and is compatible to complement CHI. The following diagram shows how AXI is used to interface an interconnect component.

There are 3 types of AXI4-Interfaces (AMBA 4.0):

AXI4 (Full AXI4): For high-performance memory-mapped requirements.
AXI4-Lite: For simple, low-throughput memory-mapped communication (for example, to and from control and status registers).
AXI4-Stream: For high-speed streaming data.

Why AXI Required?

AXI offers higher performance and throughput than AHB. There are 2 basic reasons why AXI may be faster are given below.

1. Simplex Vs Duplex Transfers

• AXI has completely independent channels for read/write, which enables full duplex mode of data transportation. That is to say read and writes can take place simultaneously, giving 2x boost over AHB in any circumstances. However this will ONLY be possible when the slave is able to process 1 read and 1 write operation simultaneously in 1 clock cycle. Which in many cases will be possible, e.g. if the slave is a dual port SRAM which can process 1 read and 1 write transaction simultaneously. Also in this example we are considering 1 Master and 1 Slave. But in case of multiple slaves, the master can send read transaction to 1 slave and write to other slave, even if the slave(s) cannot handle more than 1 transactions in single clock cycle.

• To make more clarity, in a system where there is only 1 master and only 1 slave, the slave is unable to process read and write in 1 single clock cycle simultaneously and both master and slave are in single synchronous clock domain with no clock delay between the master and the slave there wont be any difference in performance between AXI and AHB. The AXI will only consume more power and area.

2. When there are clock cycle delays between a Master and a responding slave.

• This is usually when the Master clock and slave clock is Async, and a there is a clock domain crossing bridge. In AXI case, since the system is able to issue outstanding transactions (OT), i.e. able to issue addresses without waiting for data to return, there is only a initial delay, and then the continuous flow of data follows. In AHB this is not possible. The AHB cannot issue another transaction, without first receiving the response to its only transaction, which it can issue at a time.

• It is to be noted again, that if there are no clock delays between a master and a slave, and if we assume only 1 master and 1 slave in the system, then again the AXI performance will be equal to AHB performance, if we are doing only reads or only writes.

Features:

The key features of the AXI protocol are:

• Separate address/control and data phases.
• Support for unaligned data transfers, using byte strobes.
• Uses burst-based transactions with only the start address issued.
• Separate read and write data channels, that can provide low-cost Direct Memory Access (DMA).
• Support for issuing multiple outstanding addresses.
• Support for out-of-order transaction completion.
• Permits easy addition of register stages to provide timing closure.

AXI Architecture

The AXI protocol is burst-based. Every transaction has address and control information on the address channel that describes the nature of data to be transferred.The data is transferred between master and slave using a write data channel to the slave or a read data channel to the master.In write transactions, all the data flows from master to the slave. The write response channel allow the slave to signal to the master the completion of the write operation.

WRITE Operation

                                   Fig 1: Write operation channels 

1. Initially the master initiate the transactions, primarily in the write Address channel(AW) we send the address from AXI-master to the AXI-slave and set some of the control signals such as AWLEN,AWSIZE,AWBURST etc.
2. In the next channel, write data channel(W) we send the data for that address from the AXI-master to AXI-slave.
   3.Finally from the Write Response channel(B), from the slave side, if data is successfully written in the slave address than we get the write response.
3. In the above figure we can observe that multiple write data is transferred from master to slave it depends on the burst operation.

READ Operation

                                       Fig 2: Read operation channels

1.Firstly, the master-AXI send the address from which AXI-slave it want to read the data and set some of the control signal, it is done using the Read Address channel(AR).
2. Then finally, the AXI-slave send the data of the particular address to the AXI-master through Read data channel(R).

AXI Interconnect

                                      Fig 3: AXI multiple master and multiple slave Interconnection

1. AXI Interconnect is responsible for connecting the AXI-master and AXI-Slave.
2. The AXI Interconnect act as the Slave device for AXI master and master device for the AXI slave.
3. Each slave hold the address which are connected to AXI interconnect. The AXI master is responsible for initiating the transaction whether Read or write to any of the slave depending on the address range of slaves.
4. Example in the above Figure each of the slave (i.e USB,UART,PIO) we have the starting address and ending address, whenever any of the AXI master (i.e CPU1,CPU2) want to initiate the read or write transaction to memory block i.e for slave2:UART master as to send the address within the range of slave3 and same rule follow for the other slaves in the AXI interconnection.
   5.In AXI interconnect, the every transaction come in to interconnect, the interconnect holds the decoder address table, it will first look the address of AXI transaction and route the transaction to the particular slave which holds that address.

Advantages

• Independently acknowledged address and data channels.
• Out-of-order completion of bursts.
• Exclusive access (atomic transaction)
• System level cache support.
• Access security support.
• Unaligned address & byte strobe.
• Static burst, which allows bursts to FIFO memory.
• Low power mode.

Uses

• The AXI4 protocol is used as a standard interface to connect components that wish to exchange data.
• The interface can be used to connect a single master, that generates data, to a single slave, that receives data.
• The protocol can also be used when connecting larger numbers of master and slave components.
• The protocol supports multiple data streams using the same set of shared wires, allowing a generic interconnect to be constructed that can perform upsizing, downsizing and routing operations.
• The AXI4 interface also supports a wide variety of different stream types.
• The stream protocol defines the association between Transfers and Packets.

Timing Diagram

1.Write Transaction : single data item

                                     Fig 4: Write Transaction with single data item

In this process of write transaction for a single data,we are using different channels to complete the process.

Write transaction involves following channels:
1.Write Address(AW)
2.Write(W)
3.Write Response(B)

Initially, there will be a handshake on the Write Address(AW) channel.
The handshake is where the master communicates the address of the write to the slave.
The handshake has the following sequence of events:

• The master puts the address on AWADDR and asserts AWVALID in clock cycle 2.
• The slave asserts AWREADY in clock cycle 3 to indicate its ability to receive the address value.
• The handshake completes on the rising edge of clock cycle 4.

After this first handshake,the master transfers the data to the slave on the Write(W) channel.

The data transfer has the following sequence of events:

• The slave is waiting for data with WREADY set to high in clock cycle n.
• The master puts the data on the WDATA bus and asserts WVALID in clock cycle n+2.
• The handshake completes on the rising edge of clock cycle n+3.

Finally,the slave uses the Write Response(B) channel,to confirm that the write transaction has completed once all WDATA has been received.

The write response has the following sequence of events:

• The master asserts BREADY.
• The slave drives BRESP to indicate success or failure of the write transaction, and asserts BVALID.
  The handshake completes on the rising edge of clock cycle n+4.

2.Write transaction : multiple data items

                                         Fig 5: Write transaction with multiple data items  

AXI is a burst-based protocol, which means that it is possible to transfer multiple data in a singletransaction. We can transfer a single address on the AW channel to transfer multiple data, with associated burst width and length information.

In this case, the AW channel indicates a sequence of three transfers, and on the W channel, we see three data transfers. The master drives the WLAST high to indicate the final WDATA. This means that the slave can either count the data transfers or just monitor WLAST.
Once all WDATA transfers are received, the slave gives a single BRESP value on the B channel. One single BRESP covers the entire burst. If the slave decides that any of the transfers contain an error, it must wait until the entire burst has completed before it informs the master that an error occurred.

3.Read transaction: single data item

                                           Fig 6: Read transaction with single data item  

It describes the process of a read transaction for a single data item, and the different channels used to complete the transaction.

This write transaction involves the following channels:

1. Read Address (AR)
2. Read (R)

First, there is a handshake on the Read Address (AR) channel.

The handshake has the following sequence of events:

• In clock cycle 2, the master communicates the address of the read to the slave on ARADDR and asserts ARVALID.
• In clock cycle 3, the slave asserts ARREADY to indicate that it is ready to receive the address value. The handshake completes on the rising edge of clock cycle 4. Next, on the Read (R) channel, the slave transfers the data to the master.

The data transfer handshake has the following sequence of events:

• In clock cycle n, the master indicates that it is waiting to receive the data by asserting RREADY.
• The slave retrieves the data and places it on RDATA in clock cycle n+2. In this case,because this is a single data transfer, the slave also sets the RLAST signal to high. At the same time, the slave uses RRESP to indicate the success or failure of the read transaction to the master, and asserts RVALID.
• Because RREADY is already asserted by the master, the handshake completes on the rising edge of clock cycle n+3.

4.Read transaction: multiple data items

                                           Fig 7: Read transaction with multiple data items

The AXI protocol also allows a read burst of multiple data transfer in the same transaction. This is similar to the write burst that is described in Write transaction: multiple data items.

In this example, we transfer a single address on the AR channel to transfer multiple data items, with associated burst width and length information. Here, the AR channel indicates a sequence of three transfers, therefore on the R channel, we see three data transfers from the slave to the master. On the R channel, the slave transfers the data to the master. In this example, the master is waiting for data as shown by RREADY set to high. The slave drives valid RDATA and asserts RVALID for each transfer. One difference between a read transaction and a write transaction is that for a read transaction there is an RRESP response for every transfer in the transaction. This is because, in the write transaction, the slave has to send the response as a separate transfer on the B channel.

In the read transaction, the slave uses the same channel to send the data back to the master and to indicate the status of the read operation.

If an error is indicated for any of the transfers in the transaction, the full indicated length of the transaction must still be completed. There is no such thing as early burst termination.