Various Devices Under Spartan6 Family - muneeb-mbytes/FPGABoard_edgeSpartan6 GitHub Wiki
DEVICES
What are Devices ?
Devices refer to the individual FPGA chips themselves, such as the Spartan-6 FPGA chip. These chips contain a large number of programmable logic elements, memory blocks, digital signal processing (DSP) slices, and other configurable components that can be programmed to implement a wide range of digital logic functions.
Where do I find Devices and other Architecture in Xilinx ISE?
Inside ISE, go to Tools --> Planahead --> Floorplanning
Available Devices
| Serial Number | Device Name |
|---|---|
| 1. | XC6SLX4 |
| 2. | XC6SLX9 |
| 3. | XC6SLX16 |
| 4. | XC6SLX25 |
| 5. | XC6SLX25T |
| 6. | XC6SLX45 |
| 7. | XC6SLX45T |
| 8. | XC6SLX75 |
| 9. | XC6SLX75T |
| 10. | XC6SLX100 |
| 11. | XC6SLX100T |
| 12. | XC6SLX150 |
| 13. | XC6SLX150T |
Each letter in the model name represents a specific piece of information about the device:
X: This letter denotes that the device is a Xilinx product.
C: This letter represents the generation of the FPGA. In this case, "C" stands for the "6th generation" of Xilinx FPGAs.
6: This number represents the family of the device within the 6th generation of Xilinx FPGAs. In this case, it belongs to the Spartan-6 family.
S: This letter represents the package type for the device. In this case, it is a "thin small-outline package" (TQG144).
LX: This letters represent the device speed grade. In this case, it is a "low-power, high-speed" device.
Numbers : The number represents the logic capacity of the device.
For example, In XC6SLX4, 4 represent logic cell capacity, in this case it is 4,096.
T : T in the model name indicates that it is a "thin" package option.
All 13 the devices here are a members of the Xilinx Sparton-6 family of FPGAs (Field Programmable Gate Array)
NOTE : Numbers specified in the below for each device may vary depending on the specific device variant and the design tools used.
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Logic Cells --> Used for general-purpose logic functions.
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Block RAM ---> used for on-chip storage.
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DSP Slices ---> They are specialized resources for performing digital signal processing operations such as multiply-accumulate and filtering.
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I/O Pins ---> used for interfacing with external devices.
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Clock Management ---> Clock management resources, including PLLs and DCMs, which can be used to generate and distribute clocks within the FPGA.
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Configuration ---> They can be configured using a range of methods, including JTAG, SPI, and BPI flash. Operating Temperature: The XC6SLX150 FPGA is designed to operate over a temperature range making suitable for use in high-temperature environments.
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Power Consumption ---> Actual power consumption will depend on the specific application and configuration of the FPGA.
1. XC6SLX4
Logic Cells: 3,840
Block RAM: 162 Kb
DSP Slices: No DSP Sices
I/O Pins: 72 I/O pins
Clock Management: PLLs and DCMs
Configuration: JTAG, SPI, and BPI flash
Operating Temperature: -40°C to 100°C
Power Consumption: 0.34W at 100MHz
2.XC6SLX9
Logic Cells: 9,152
Block RAM: 486 Kb
DSP Slices: 18
I/O Pins: 93
Clock Management: PLLs and DCMs
Configuration: JTAG, SPI, and BPI flash.
Operating Temperature : -40°C to 100°C
Power Consumption: 0.54W at 100MHz
3. XC6SLX16
Logic Cells: 14,579
Block RAM: 576Kb
DSP Slices: 24
I/Os: 116
Clock Management: Phase-locked loops (PLLs) and digital clock managers (DCMs)
Configuration: serial configuration interface (SPI)
Power: 1.8W
| Packages under XC6SLX16 |
|---|
| CSG324 |
| FTG256 |
| CSG225 |
| CPG196 |
4. XC6SLX25
Logic Cells: 24,051
Block RAM: 360Kb
DSP Slices: 80
I/O Pins: 200
Clock Management: The FPGA has a sophisticated clock management system that can generate multiple clock signals with different frequencies and phases.
Configuration: JTAG, SPI, and BPI
Power Consumption: 1.3 W at 100 MHz
| Packages under XC6SLX25 |
|---|
| CSG324 |
| FGG484 |
| FTG256 |
5. XC6SLX25T
Logic Cells: 24,051
Block RAM: 576 KB
DSP Slices: 20
I/Os: 185
Power consumption : Static Power 0.5 W at 85°C , while the dynamic power consumption can range from 0.25 W to 2.5 W Static power - current flows through transistor when there is no current, Dynamic Power - Short Circuit power.
Package: The XC6SLX25T FPGA is available in a variety of different packages
| Packages Under |
|---|
| FTG256 |
| CSG225 |
| FG256 |
| TQG144 |
| CPG196 |
6. XC6SLX45
Logic Cells: 43,661
Clocks: 6,960
Block RAM: 1,036 KB
DSP Slices: 40
I/Os: 315
Power Consumption : Static around 0.7 W at 85°C and Dynamic power 0.35 W to 3.5 W
| Packages Under |
|---|
| FTG256 |
| FGG484 |
| CSG324 |
| TQG144 |
| CPG196 |
7. XC6SLX45T
Logic Cells: 43,661`
Block RAM: 1.1 Mb
I/O Pins: 324 I/O pins
Clock Management: Digital clock managers (DCMs) and Phase-locked loops (PLLs)
Power Consumption: 2.2 W
Package: Plastic ball grid array (PBGA) package
8. XC6SLX75
Logic Cells: 74,637
Block RAM : 1.8 Mb
I/O Pins: 484
Clock Management: Digital clock managers (DCMs) and phase-locked loops (PLLs)
Power Consumption: 3.4 W
Package: Flip-chip ball grid array (FCBGA) package
9. XC6SLX75T
Logic Cells: 74,637
Block RAM: 1.8 Mb
I/O Pins: 484
Clock Management: Digital clock managers (DCMs) and phase-locked loops (PLLs)
Power Consumption: 3.4 W
Package: Plastic ball grid array (PBGA) package and flip-chip ball grid array (FCBGA) package.
10. XC6SLX100
Logic cells: 101,261
Block RAM: 4.9 Mb
DSP slices: 240 dedicated digital signal processing (DSP) slices
I/O pins: 324
Clocking resources: Eight Digital Clock Managers (DCMs)
Configuration memory: Loading a bitstream into the device's configuration memory
Package options: FG484, FG676, and FF1156 packages
11. XC6SLX100T
Logic Cells: 101,261
Block RAM: 4,860 Kb.
DSP Slices: 180
I/O Pins: 316
Clock Management Tiles (CMTs): There are 4 CMTs. The CMTs are used to generate and distribute clock signals throughout the device.
Maximum Internal Clock Frequency: 500 MHz
JTAG Ports: It has 1 JTAG Ports.
Configuration Options: There are 3 configuration mode namely Master Serial, Slave Serial, SelectMAP, JTAG. The Master Serial mode is the most commonly used configuration mode, and it allows the FPGA to be configured using a single serial configuration interface. The Slave Serial mode enables multiple FPGAs to be configured in a daisy-chain fashion. The SelectMAP mode uses a parallel interface to configure the FPGA.
Package: Flip-chip BGA (27x27 mm). Flip chip packaging is a type of semiconductor packaging in which the semiconductor die is mounted face-down (i.e., flipped) onto the packaging substrate.
12. XC6SLX150
Logic Cells: 147,443
Block RAM: 8.18 Mb
DSP Slices: 360
I/O Pins: 622 I/O pins
Clock Management: PLLs and DCMs
Configuration: JTAG, SPI, and BPI flash
Operating Temperature: -40°C to 100°C
Power Consumption: 1.1W at 100MHz
13. XC6SLX150T
Logic Cells: 147,443
Block RAM: 8.18 Mb
DSP Slices: 360 DSP slices
I/O Pins: 622 I/O pins
Clock Management: PLLs and DCMs
Configuration: JTAG, SPI, and BPI flash
Operating Temperature: -40°C to 100°C
Power Consumption: 1.1W