User Constraints - muneeb-mbytes/FPGABoard_edgeSpartan6 GitHub Wiki
User Constraints involves 4 steps:
| Sr.no | TOPICS |
|---|---|
| 1 | Create Timing Constraints |
| 2 | I/O Pin Planning(PlanAhead)-Pre-Synthesis |
| 3 | I/O Pin Planning(PlanAhead)-Post-Synthesis |
| 4 | Floorplan Area/IO/Logic(PlanAhead) |
Before understanding the steps involved, let us first understand what PlanAhead is?
PlanAhead is a software tool provided by Xilinx that is used for planning, analyzing, and optimizing designs for Xilinx FPGAs. PlanAhead provides a graphical user interface (GUI) for the creation and analysis of hierarchical designs, including IP integration, power analysis, and timing closure. It is an important tool in the FPGA design process, especially for larger and more complex designs.
It is mainly used for I/O pin planning and floorplanning.
After running the PlanAhead the files that are created is shown below:
PlanAhead software for I/O Pin Planning involves a display of FPGA package which shows all the pins and user can select a set of pins or individual pin to see the pin numbers.
The pin numbers can be changed by following the below procedure:
- Under scalar ports (Scalar ports are single-bit input or output ports in a digital circuit. In contrast, a vector port is a multi-bit input or output port), select the port whose pin number is to be changed
- Click on the existing pin number in the column called Site
- From the drop down, select the required pin number
- In the column called Fixed, Uncheck the box and then recheck
- Click on the save option or click Ctrl+S
Once this is done, the changes will be reflected on to the corresponding full adder UCF file
"planAhead_run" refers to a folder or directory created by the Xilinx PlanAhead tool during a synthesis or implementation run. The folder contains the output files generated by the tool, such as reports, bitstream files, and other design files. The naming convention for the folder is usually "planAhead_run_#", where "#" is a number that increments for each new run. This allows you to keep track of multiple runs of the tool and compare the results.
pa.fromHDL is a method in PlanAhead software tool used for creating a PlanAhead project from Hardware Description Language (HDL) files. It allows the user to import HDL source files, such as Verilog or VHDL, and automatically generate a PlanAhead project with the corresponding design hierarchy. This method is useful for users who have existing HDL code and want to create a PlanAhead project for further implementation, synthesis, or simulation.
This is a PlanAhead launch script written in TCL (Tool Command Language) used for pre-synthesis planning in Xilinx FPGA design flow. The script performs various tasks like creating a new project, setting project parameters, adding source files, setting constraints, and opening the RTL design for the specified target device.
planAhead_pid3041 is a temporary file created by PlanAhead, Xilinx's software tool for planning, analyzing, and optimizing FPGA designs. This file is automatically created after closing the planahead. It is a Debug File which is a log file about internal application errors that are occurred in PlanAhead. The name of the file includes "pid3041" which is a unique identifier assigned to each PlanAhead process running on a computer. Pid refers to process ID.
Floorplanning is the process of placing different logic modules and components of a design onto an FPGA device. It involves partitioning the FPGA device, creating power and clock networks, and placing the different components in the appropriate partitions. The goal of floorplanning is to optimize the placement of different components to achieve the best possible performance and utilization of the FPGA device.
The device represents the detailed architecture containing slices, LUTs, MUX, Gates, pins, etc in spartan 6 FPGA.
We can look at the placement of the pins by clicking on the pin name under Primitives. The corresponding pin is then highlighted on the device
By right clicking on to the port we can make unplace the port or select a new port in 2 ways
- Place I/O ports in Area
- Place I/O ports sequentially
The changes will be reflected on to the UCF File.
Files generated after floorplanning are:
It contains a subdirectory called PlanAhead-2641-localhost.localdomain. PlanAhead-2641-localhost.localdomain is a process ID folder that is generated by the PlanAhead software tool. When PlanAhead is launched, it starts a process and assigns a unique ID to it. This ID is used to keep track of the process and any related information, such as log files, temporary files, and other data. In this case, 2641 is the process ID, and localhost.localdomain is the name of the computer on which the PlanAhead tool is running.
It further contains a subdirectory called ngc2edif. ngc2edif is a command-line tool provided by Xilinx to convert a pre-compiled NGC (Native Generic Circuit) netlist file to an EDIF (Electronic Design Interchange Format) netlist file. EDIF is a standard file format for representing electronic designs, and it is used by many EDA tools to exchange data between each other. ngc2edif is typically used when you want to integrate an existing design into a larger system or when you want to use a third-party tool that requires an EDIF netlist file as input.
NGC2EDIF file
EDIF File
