Synthesize XST - muneeb-mbytes/FPGABoard_edgeSpartan6 GitHub Wiki
| Sr.no | TOPICS |
|---|---|
| 1 | View RTL Schematic |
| 2 | View Technology Schematic |
| 3 | Check Syntax |
| 4 | Generate Post-Synthesis Simulation model |
View RTL Schematic
For this we can double click on the "view RTL schematic" and then add full adder to the selected elements and click Create schematic. This will provide the created symbol or block of done during create symbol step. On double clicking the block we can view the RTL schematic. RTL (Register Transfer Level) is a level of abstraction in digital design that describes the flow of data between registers and the operations performed on that data. A schematic at the RTL level typically shows the interconnection of registers, multiplexers, arithmetic and logic units, and other components that make up a digital circuit.
View Technology Schematic
A technology schematic can show the physical layout of a chip or integrated circuit (IC), including the location and interconnections of individual components LUTs, Buffers etc,. It is obtained in the same way as RTL Schematic by performing the procedure.
LUT3 represents a 3 input LUT and each LUT has only one output. By double clicking on each LUT we can view the
The files generated on running Synthesis XST is displayed below:
.cmd_log File
There will not be a new command log file created, but the exisiting file gets updated. For every operation you perform in ise Xilinx like synthesis, implement design and generate programming etc, the commands that are used to run that processes are stored in .cmd file.
For example, if you tap on synyhesis option ,then a command line shown below will get stored.
xst -intstyle ise -ifn "/home/ise/new1/sevensmt.xst" -ofn
.ngc File
It is a post synthesis netlist file This file is the final output of the synthesis process, it has the synthesized gate level netlist of the design.it is a binary file and not a human readable. This file can be used as the input fie to the further process involved after synthesis process. .ngc file appears in the ISE suite during view technology schematic. The NGC file created in the folder can be reused to implement the full adder without synthesising i.e., it provides a pre-synthesised project.
.ngr File
As .ngc is the final file generated after synthesis process, whereas .ngr is the file which is generated in between synthesis process, that means it is a intermediate file generated during synthesis that contain design hierarchy and how they are interconnected. NGR file appears in ISE suite during view RTL schematic.
PROJECT File
This file specifies the list of the source file , that means it includes the list of velilog/VHDL source file. The content which was present in our case was: Verilog work ā../fulladder/full_adder.vā, Which means it just gives the location of .v files
.syr File
The file which is generated during synthesis process contains synthesis report for the design, it has information about all the logic elements used, flipflops used etc . it also shows various constraints, its like a summary file.
Webtalk_pn.xml
This file contains mapping information between logical(RTL) and physical (gate level) elements of the design
.xst ( xilinx synthesis technology) File
This is a Tcl script that contains Xilinx ISE tool options for the Xilinx Synthesis Technology (XST) tool. The XST tool is used to synthesize a design specified in a hardware description language (HDL) into a gate-level netlist that can be used for implementation on a specific FPGA. It contains TCL commands that define the whole synthesis process.
.xrpt file
The .xrpt file is a project report generated by the Xilinx ISE Design Suite during the synthesis process. It contains information about the synthesis run, such as the design hierarchy, synthesis options, and output products. This report can be useful for analyzing and debugging the synthesis process and can provide insight into any issues that may have arisen during the process.
The .xrpt file is generated automatically by the Xilinx ISE Design Suite and is saved to the same directory as the project files. The file can be viewed using any text editor or it can be imported into the Xilinx Project Navigator to be viewed in a more user-friendly format.
LSO File
It contains the specification of the target library. In our case the target library is "work".
