Spartan-6 FPGA Architecture

There are three basic building blocks of digital logic:

• CLBs (Configurable Logic Blocks)
• Slices
• Logic Cells.

CLB (Configurable Logic Block)

A CLB is the largest building block of digital logic in a Spartan-6 FPGA. It contains multiple Slices, along with other components such as Carry Logic. A CLB can implement more complex and larger functions than a Slice or Logic Cell.

• Each CLB has 2 slices
• These two slices do not have direct connections to each other, and each slice is organized as a column

Slice

A Slice is a smaller building block of digital logic that is contained within a CLB. It contains a four 6-input Look-Up Table (LUT), which can be programmed to implement any logic function of up to 6 inputs, and a D Flip-Flop (FF), which can be programmed to implement any type of sequential logic. Slices are highly configurable and flexible and can be cascaded to create complex logic functions.

Each slice in Spartan-6 consists of four 6-input Look-Up Tables (LUTs) and eight flip-flops.

6-input LUT can be two 5-input LUTs with common inputs

Logic cells

A Logic Cell is a basic building block of digital logic that can be implemented using a variety of technologies, including LUTs, Multiplexers, Flip-Flops, and other components. Logic Cells can be used to implement a wide range of digital functions, including combinational and sequential logic. In Spartan-6 FPGAs, Logic Cells are typically used to implement small and simple functions

Difference between CLB, Slice & Logic cells

The main differences between CLBs, Slices, and Logic Cells in Spartan-6 FPGAs are their size and the complexity of the functions they can implement. CLBs are the largest and most complex building blocks, while Slices are smaller and more flexible, and Logic Cells are the smallest and simplest building blocks.

Block RAM

• Block RAMs (or BRAM) stands for Block Random Access Memory
• Block RAM is a dedicated memory resource that can be used to store large amounts of data inside FPGA
• Block RAMs can be used in a variety of applications, including as data buffers, lookup tables, and frame buffers.
• Usually the bigger and more expensive the FPGA, the more Block RAM it will have on it
• Each FPGA has a different amount of Block RAM, so depending on our application we may need more or less Block RAM.

DSP48 (Digital Signal Processing 48-bit)

• DSP48 (Digital Signal Processing 48-bit) is a dedicated hardware block in Xilinx Spartan-6 FPGAs that is optimized for implementing digital signal processing functions.
• It consists of 25-bit multipliers, an adder/subtractor, and a 48-bit accumulator, as well as a range of other supporting features.
• DSP48 blocks can be used to implement a wide range of digital signal processing functions, including finite impulse response (FIR) filters, infinite impulse response (IIR) filters, fast Fourier transforms (FFT), etc.
• One of the key advantages of using DSP48 blocks in Spartan-6 FPGAs is their performance and efficiency.
• The number of DSP slices available in an FPGA varies depending on the specific device, and the number of slices required for a particular application will depend on the complexity of the processing required.

I/O Blocks

• I/O Blocks (IOBs) are a type of programmable logic block that handles input and output operations.
• They provide the interface between the programmable logic and the package pins, allowing the FPGA to communicate with the outside world.
• These pins are used to provide input/output (I/O) functionality for the FPGA, allowing it to interact with other digital devices or sensors.
• Each Spartan-6 device contains either four or six I/O banks depending on device size and package

Clock management Tile (CMT)

Clock management in the Spartan-6 FPGA refers to the set of features and resources that are used to manage clock signals in a design.

Some of the key clock management resources in the Spartan-6

• Digital Clock Managers (DCMs): DCMs are used to generate and clean up clock signals. They can be used to adjust the phase and frequency of a clock signal, as well as to multiply or divide its frequency.

• Phase-Locked Loops (PLLs): PLLs are used to generate stable, high-quality clock signals. They can be used to generate high-frequency clock signals from a lower-frequency input clock.

• Input Delay Blocks (IDELAYs): IDELAYs are used to adjust the phase of incoming clock signals in order to meet timing requirements. They can be used to align multiple clock domains or compensate for skew between different parts of the design.

• Output Delay Blocks (ODELAYs): ODELAYs are used to adjust the phase of outgoing clock signals in order to meet timing requirements. They can be used to align clock signals with data signals or compensate for delays throughout the design.

Power Management

The Spartan-6 FPGA includes a range of power management features, including clock gating, power gating, and dynamic voltage scaling. These features allow the device to reduce power consumption when certain parts of the design are not being used or when the device is operating at a lower performance level.

• Clock gating: Clock gating is a technique used to reduce power consumption in digital circuits by disabling the clock signal to parts of the circuit that are not currently being used. In clock gating, a control signal is used to enable or disable the clock signal to specific parts of the circuit. By disabling the clock signal to unused parts of the circuit, the power consumption of the circuit is reduced.

• Power gating: Power gating is a power management technique used to reduce power consumption by selectively shutting down power to parts of the FPGA that are not currently being used. The power gating feature in Spartan-6 FPGAs is implemented using a power gate transistor that is added to the power supply path of the circuit. When a logic slice, block RAM, or DSP slice is not in use, the power gate transistor is turned off, cutting off the power supply to that part of the circuit.

• Dynamic voltage scaling: Dynamic voltage scaling (DVS) is a power management technique used in Spartan-6 FPGAs to adjust the voltage supply to the FPGA in real time, based on the operational requirements of the design. By reducing the supply voltage to the FPGA during periods of low activity, designers can significantly reduce the power consumption of the FPGA. In Spartan-6 FPGAs, dynamic voltage scaling is implemented using a real-time voltage regulator that can adjust the supply voltage to the FPGA.