Slide Switches and Push Buttons - muneeb-mbytes/FPGABoard_edgeSpartan6 GitHub Wiki

Slide Switches

  • Slide switches are a type of input device commonly used in digital systems to provide user input to the FPGA. In this case, the UCF file specifies the physical locations of the slide switches and assigns them to their corresponding signal names or nets.

NET "sw<0>" LOC = p22; #LSB

NET "sw<1>" LOC = p21;

NET "sw<2>" LOC = p17;

NET "sw<3>" LOC = p16;

NET "sw<4>" LOC = p15;

NET "sw<5>" LOC = p14;

NET "sw<6>" LOC = p12;

NET "sw<7>" LOC = p11;

NET "sw<8>" LOC = p10;

NET "sw<9>" LOC = p9;

NET "sw<10>" LOC = p8;

NET "sw<11>" LOC = p7;

NET "sw<12>" LOC = p6;

NET "sw<13>" LOC = p5;

NET "sw<14>" LOC = p2;

NET "sw<15>" LOC = p1; #MSB

  • Each line in the statement corresponds to a specific slide switch, with the slide switch number specified in angle brackets "< >".

  • For example, "NET "sw<0>" LOC = p22; #LSB" specifies that slide switch 0 (the least significant bit, or LSB) is located at pin p22 of the FPGA. The remaining lines similarly specify the physical locations for slide switches 1 through 15.

  • The "LOC" keyword specifies the physical pin location for the corresponding signal or net, while the "#" character is used to add comments to the code.

  • In this case, the comments indicate which slide switch corresponds to each line, and which one is the most significant bit (MSB).

Push Buttons

  • In an FPGA board, push buttons are a type of input device that allow the user to send signals or trigger actions by pressing a button.

  • They are a useful input device in FPGA designs, allowing the user to interact with the FPGA board and trigger specific actions or operations.

  • With proper configuration and integration into the FPGA design, push buttons can help make FPGA-based systems more flexible and user-friendly.

NET "PB[4]" LOC =P45;

NET "PB[3]" LOC = P44;

NET "PB[2]" LOC = P43;

NET "PB[1]" LOC = P41;

NET "PB[0]" LOC = P40;

  • PB[4] is the name of the signal.

  • LOC =P45 is a physical constraint that specifies the pin location on the FPGA board where this signal should be connected.

  • The above statement tells the synthesis tool to assign the signal PB[4] to the physical pin P45 on the FPGA board.

  • Similarly the signals PB[3] , PB[2], PB[1] and PB[0] are assigned to the physical pins namely P44, P43, P41 and P40 on the FPGA board respectively.

  • This is an important step in designing hardware since it ensures that signals are connected to the correct pins on the board.