Phase Locked Loop - muneeb-mbytes/FPGABoard_edgeSpartan6 GitHub Wiki
Phase_Locked Loop (PLL)
A phase-locked loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. The main purpose of a PLL circuit is to synchronize an output oscillator signal with a reference signal.
A simple Block diagram for a Phase Locked loop is given below.
The Components of a Phase Locked Loop are
- Phase Detector
- Low Pass Filter (LPF) also called Loop Filter
- Voltage Controlled Oscillator (VCO)
Phase Detector The phase detector compares the phase of two input signals and produces an output voltage that is proportional to the phase difference between them. In a PLL, one input to the phase detector is the reference signal and the other input is the feedback signal from the VCO.
Low Pass Filter of Loop Filter The loop filter is a low-pass filter that filters the output of the phase detector to remove any high-frequency noise and produce a DC voltage that controls the VCO. The loop filter is designed to provide stable and precise control of the VCO.
Voltage Controlled Oscillator The VCO is an oscillator whose output frequency is controlled by a DC voltage input. The output frequency of the VCO is proportional to the input voltage from the loop filter.
Phase Locked loop in FPGA
PLL's are used in FPGA's to increase the frequency of the Clock signal.
Suppose we have a clock signal of 12MHz and want to multiply it. Clock 12 MHz is given as Reference signal at point A. Initially the output of VCO will be 12MHz at point B and will be sent as a feedback. In the feedback circuit a Frequency divider is used. Click for more info on Frequency Divider. The frequency divider will divide the frequency, In this case by a factor of 4. Clock of 3MHz will be given as input to the Phase detector at point C. Now the Phase detector that will compare both the signals and give the output. This is where the VCO will multiply the clock by a factor of 4 to match signal at A with signal at C.