Let's Learn Vivado - muneeb-mbytes/FPGABoard_edgeSpartan6 GitHub Wiki

What is Vivado?

Vivado is a powerful and widely used tool for designing, synthesizing, simulating, and implementing digital circuits on FPGA.

Advantage:

a)It has System Verilog

b)Automatically checks for the Syntax

the syntax is correct so it is showing green square . If the Syntax is wrong then there will be a red square

c)You can create block design

Click here for tutorials

d) This is a new version and some of the device families that are supported by Vivado are Spartan 7,Artix-7,Kintex-7,Virtex-7,UltraScale,Zynq-7000

e) Vivado supports a variety of System on Chip (SoC) for example Zynq-7000, UltraScale+ MPSoC,Versal ACAP

Steps:

1.First Install vivado.

2.Click on create project

  1. In the project wizard, specify the project name, location, and select the desired project settings
  1. Select "RTL Project" and click "Next". RTL project because you will be able to add sources, create block designs in IP integrator, generate IP, run RTL analysis, synthesis, implementation, design planning and analysis.
  1. In the "Add Sources" screen, if you already have the code then click on add files if not click on create file. We will click "Create File" to create a new design source file.

Choose the desired file type for your design, such as VHDL or Verilog, and click "Next"

  1. click "Create File" to create a new constraints file.
  1. Click on family and choose one according to your reqirements.

10.Specify the Board your Working on

13.In Vivado, a constraint file (also known as a "XDC file") is a file that contains timing, placement, and routing constraints for a particular FPGA design. These constraints are used to guide the Vivado tools during synthesis, implementation, and bitstream generation to ensure that the design meets timing requirements and is placed and routed optimally.

Design Source is where you write your code ( verilog , VHDL, system verilog)

Simulation Source is where you write testbench.

  1. If you want you can initialize your input here.

23.Since we did not add testbench we will give values to A and B.

  1. We will add testbench file now
  1. Write your testbench here
  1. Click on drop down and select schematic

Reference:

https://www.youtube.com/watch?v=bw7umthnRYw

How to create a block design??

  1. Click on the "Create Block Diagram" button to launch the Block Diagram Editor.
  1. Name your design
  1. To add a block, click on the "+ Module" button
  1. Select the desired block from the list. For example we will select Adder/Subtractor
  1. If you want to change the input width , click on the block name which is above the block.
  1. To change the input type and input width press Manual (it will shift from auto to manual) you can set the input width of your choice.
  1. We will be adding unsigned numbers(you can add signed numbers as well).
  1. Here we have taken 32 bit input