Implementation steps - muneeb-mbytes/FPGABoard_edgeSpartan6 GitHub Wiki

Before diving into implementation process, let us first understand some terminologies

What is a Netlist?

In electronic design, a netlist is a description of the connectivity of an electronic circuit. In its simplest form, a netlist consists of a list of the electronic components in a circuit and a list of the nodes they are connected to. We have different types of netlists of which 2 are required in implementation:

• RTL Netlist
• Gate Level Netlist(Post synthesis netlist) The RTL netlist provides a list of components that will be used in the physical implementation of the design. The RTL netlist specifies the interconnections between the registers and the combinational logic, as well as any external inputs and outputs of the design. The post-synthesis netlist provides a complete specification of the design that is ready for physical implementation on a specific hardware platform. It lists the gates, registers, and wires that will be used in the final implementation, along with their connectivity and timing information.

Now let us take the example of full adder to understand implementation steps. Let the project name be full_adder, verilog code file be adder.v and ucf file be adder_ucf.ucf The project representation and steps involved in implementation can be seen below:

_xmsgs

_xmsgs folder holds message files. They are text files that contain messages generated by the ISE software during the FPGA design process, including synthesis, implementation, and programming. Initially before synthesis it contains only pn_parser.xmsgs file. It may include information such as the location of syntax errors, warnings about unsupported syntax, or updates on the progress of the parsing process. The parser msg file without any errors looks like below initially,

Even before synthesis the parser msg file looks for errors in the verilog code and updates it in the file. The folder keeps getting updated with newer msg files as we proceed.

ipcore_dir

In Xilinx ISE and Vivado design tools, an IP Core directory is a location where reusable intellectual property (IP) blocks can be stored. It is a subdirectory, containing IP (intellectual property) cores used in the design. IP cores are pre-designed and pre-verified blocks of logic that can be easily integrated into larger designs, reducing the time and effort required for design and verification. Since our full adder project does not contain any of the pre-defined IPs, the ipcore directory will be empty.

(parse error: without compiling the code, if the error is generated them it is parse error)

iseconfig

It contains XREPORT files and PROJECTMGR file. They provide the overall ISE configuration and status of the project

Verilog File type (adder.v)

It is the verilog file which contains the verilog code for specific operation. In our case it contains verilog code for full adder.

adder_summary and full_adder_summary

The html documents of summary will provide the overall summary of synthesis and implementation which will initially be empty and will get updated.

.ucf file

UCF stands for User Constraints File. It is a file format used in the Xilinx ISE software suite for specifying the pin locations, I/O standards, and other constraints for an FPGA design. The UCF file is a plain text file that can be edited using any text editor.

.xise file

XISE stands for Xilinx Integrated Software Environment. The XISE file contains information about the FPGA design project, including source code files, simulation settings, device constraints, and other project-specific settings. It is essentially a container that organizes all the files and settings needed for a specific FPGA design project.

.gise file

The GISE file provides tracking of generated files along with other information. This file keeps getting updated with new file information as we run new steps.

The implementation steps involved are:

Sr.no	TOPICS
1	Design Utilities
2	User Constraints
3	Synthesize XST
4	Implement Design
5	Generate Programming File