Implementation

Implementing a design in Xilinx 14.7 involves taking the RTL or post-synthesis design and converting it into a physical configuration file that can be programmed onto an FPGA.

Why Implementation?

Implementing designs on an FPGA is necessary because it is the process by which the design is turned into a physical hardware prototype that can be tested and evaluated. There are three main sub-divisions:

(a) Translate

(b) Map

(c) Place and Route

Translate:

The translate option is necessary because the post-synthesis netlist generated by the synthesis process is in a format that cannot be directly used by the implementation tools. By using the Translate option, the netlist is optimized and converted into a format that can be used by the subsequent stages in the implementation flow, such as mapping and place-and-route. Note that the translate process is not the same as the synthesis process, which converts the RTL design code into a post-synthesis netlist. The translate process is a separate step that operates on the post-synthesis netlist to generate the intermediate files needed for the implementation flow.

Generate Post Translate:

Generate Post-Translate" refers to the process of generating output files that represent the design after it has been optimized and mapped to the target FPGA device during the "Translate" process. The main difference between the "Translate" and "Generate Post-Translate" options in Xilinx ISE is that the Translate process converts the post-synthesis netlist into a format that can be used by the implementation tools, while the Generate Post-Translate process generates output files that represent the design after it has been optimized and mapped to the target FPGA device during the Translate process.

Map:

Map means taking your design and fitting it to a specific FPGA or CPLD device. This involves assigning each part of your design to a specific location on the device, connecting the parts in an efficient way, and optimizing the design to use as little power as possible. Finally, you create a file that tells the device how to implement your design.

Place and Route:

It is a process of mapping the logic of a design to the physical resources of the target FPGA device, and routing the interconnect between these resources. During the place-and-route process, the implementation tool takes the following steps:

Placement: The implementation tool maps the logic elements of the design to the physical resources of the target FPGA device. The placement process aims to minimize the delay of the design by placing the logic elements close to their required inputs and outputs.

Routing: The implementation tool routes the interconnect between the placed logic elements. The routing process aims to minimize the delay and area of the design by selecting the optimal routing paths.

Files generated during Implementation:

Ngo (Native Generic Object):

Ngo has a netlist file and the netlist file shows the path with an OK message

Eg: /home/ise/ISE/and_gate/and_gate.ngc 1679531629 OK

Netgen:

It contains a synthesis folder which again consists of 2 files:

(i) NLF file: which contains version, memory usage along with errors and warnings.

(ii) V file: It is simply like a user manual that contains vendor name, Input and output file, path, purpose of the file along with the code.

Xlnx_auto _0_xdb:

This contains cst file (Constraint Set) which is plain text that can be edited contains info like clock frequency, input output delay constraints.

Bld (Berkeley Logic interchange Format):

BLD files are project files that contain information about the code, libraries, and other resources used in the project. In general, BLD files are used as project files or output files that contain information such as configurations, and output logs, number of errors, warnings, partitions status.

Ncd (Native Circuit Description):

The NCD file contains all the necessary information to configure an FPGA with the design created in the Xilinx FPGA development tools.

Ngd (Next Generation Design):

Which converts the RTL (Register Transfer Level) design code written in a hardware description language such as VHDL or Verilog into a gate-level netlist that can be implemented on an FPGA device. The NGD file is used as input to the place-and-route tool, which maps the synthesized netlist onto the physical resources of the target FPGA device.

Full_adder_Pad file:

This file is designed to be imported into a spreadsheet program such as Microsoft Excel for viewing, printing and sorting. It is used display pin number, name, usage etc using tables.

Full _adder_pad (Microsoft Excel):

This file is designed to be imported into a spreadsheet program such as printing & sorting. It is used display pin number, name, usage etc using tables.

Full_adder_pad (txt):

This file is designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.

Par (Place & Route):

Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". It has got initial temperature & voltage along with device utilization summary.

Pcf (physical Constraint File):

It is a command used by the Xilinx implementation tool to guide the place and route process, ensuring that the design meets the specified constraints.

Written by: Map P.20131013 on Thu Mar 23 00:37:16 2023

ptwx:

A PTWX file refers to the timing report file during the implementation process of a digital design. The PTWX file is an important tool for designers to debug and optimize their designs for timing performance. It can help identify timing issues in the design and provide insight into how to improve timing performance by adjusting design constraints or making design changes. Timing information like raising time, hold time etc...

Twr (Timing Reports):

It contains datasheet report of clocks, inputs, outputs along with the delays. All values displayed in nanoseconds (ns).

Twx (Timing waveform eXtension):

It contains detailed timing waveform analysis information. It can be used to identify timing violation (displays True, False), optimize timing constraints.

Unroutes files:

It displays whether the signals are routed or not. i.e. All signals are completely routed.

XPI (Crossed Platform Install):

It contains program, state and Time Specification details

PROGRAM=PAR: This specifies the programming mode for the Xilinx device. "PAR" stands for "place and route," which is a step in the FPGA design flow where the logic elements in the design are placed on the FPGA device and then interconnected (routed) to implement the desired functionality.

STATE=ROUTED: This indicates the current state of the Xilinx implementation project. "ROUTED" means that the place and route step has been completed, and the design has been routed on the FPGA device.

TIMESPECS_MET=OFF: This specifies whether timing specifications (constraints) have been met in the design. "OFF" means that timing specifications are not being checked or enforced. This can be useful during initial design iterations when timing constraints are still being refined or when the design is being debugged. Once the design is stable, timing constraints should be specified and enforced to ensure reliable operation of the design.

Map File:

Map file is a text file that contains information about the placement of the design's logical elements (e.g., cells, registers, memory blocks) onto physical locations (e.g., slices, pins, routing resources) of the target FPGA device. Also contains a list of all the logic elements in the design, timing specifications and their corresponding physical locations on the FPGA device. The number of inputs and outputs for each logic element. The routing resources, resource utilization statistics, such as the percentage of FPGA resources used by the design used to connect the logic elements.

Running timing-driven placement...

Total REAL time at the beginning of Placer: 4 secs

Total CPU time at the beginning of Placer: 3 secs

NGM File (Netlist Generated for Macro):

An NGM (Netlist Generated for Macro) file is a specialized netlist file that contains the information needed to implement and program a specific macro in an FPGA design. A macro can be a simple digital logic element, such as a flip-flop or an adder, or a more complex module, such as a memory block, a communication interface unit. This file is automatically created by Xilinx's implementation tools when a macro is added to the design. The NGM file contains information that is needed to configure the macro, such as how it is connected to other circuit elements and how it should be programmed.

XRPT:

The data in this file is primarily intended for consumption by Xilinx tools. The structure and the elements are likely to change over the next few releases. This means code written to parse(breaking the code into keywords, variables and analysing this file will need to be revisited each subsequent release.

Par_usage_statistics:

This is a HTML file that contains non vcc ground signals, CPU time taken by each phase of implantation process and fanout (number of connections single output can drive)