GPIO and VGA Port - muneeb-mbytes/FPGABoard_edgeSpartan6 GitHub Wiki

NET "GPIO[0]" LOC = "p75";

NET "GPIO[1]" LOC = "p74";

NET "GPIO[2]" LOC = "p67";

NET "GPIO[3]" LOC = "p66";

NET "GPIO[4]" LOC = "p62";

NET "GPIO[5]" LOC = "p61";

NET "GPIO[6]" LOC = "p59";

NET "GPIO[7]" LOC = "p58";

NET "GPIO[8]" LOC = "p57";

NET "GPIO[9]" LOC = "p56";

NET "GPIO[10]" LOC = "p55";

NET "GPIO[11]" LOC = "p51";

NET "GPIO[12]" LOC = "p50";

NET "GPIO[13]" LOC = "p48";

NET "GPIO[14]" LOC = "p47";

NET "GPIO[15]" LOC = "p46";

• The statements in the FPGA UCF file define the pin locations for the General-Purpose I/O (GPIO) port and the CMOS Camera Interface in the FPGA design.

• By defining the pin locations for the GPIO port and CMOS Camera Interface, the UCF file tells the FPGA how to communicate with external devices connected to these ports.

• This information is critical for the successful implementation of the FPGA design.

NET "GPIO[0]" LOC = "p75";

• This line defines the signal name for the first pin of the GPIO port as "GPIO[0]" and assigns it to the physical pin location p75 on the FPGA board.

NET "vga_R<0>" LOC = "p95";

NET "vga_R<1>" LOC = "p94";

NET "vga_R<2>" LOC = "p93";

NET "vga_R<3>" LOC = "p92";

NET "vga_G<0>" LOC = "p100";

NET "vga_G<1>" LOC = "p99";

NET "vga_G<2>" LOC = "p98";

NET "vga_G<3>" LOC = "p97";

NET "vga_B<0>" LOC = "p105";

NET "vga_B<1>" LOC = "p104";

NET "vga_B<2>" LOC = "p102";

NET "vga_B<3>" LOC = "p101";

NET "vga_HSync" LOC = "p111";

NET "vga_Vsync" LOC = "p112";

• The first four sentences assign locations to the four red color signal pins (vga_R<0-3>) of the VGA port on the FPGA board. These pins are connected to pins p95, p94, p93, and p92, respectively.

• The next four sentences assign locations to the four green color signal pins (vga_G<0-3>) of the VGA port on the FPGA board. These pins are connected to pins p100, p99, p98, and p97, respectively.

• The following four sentences assign locations to the four blue color signal pins (vga_B<0-3>) of the VGA port on the FPGA board. These pins are connected to pins p105, p104, p102, and p101, respectively.

• The last two sentences assign locations to the Horizontal Sync (vga_HSync) which is a timing signal used to synchronize the horizontal scanning of the image displayed on the screen, while the Vertical Sync signal (vga_Vsync) is used to synchronize the vertical scanning of the image of the VGA port on the FPGA board.

• These signals are connected to pins p111 and p112, respectively, and are used to synchronize the display of the video signal with the refresh rate of the monitor.