Design Utilities - muneeb-mbytes/FPGABoard_edgeSpartan6 GitHub Wiki

Design utilities involves 3 steps

Sr.no	TOPICS
1	Create schematic symbol
2	View command line log file
3	View HDL instantiation template

After running the three steps in design utilities i.e, create schematic symbol, view command line log file and view HDL instantiation template, the new files that get generated is displayed below:

Create Schematic Symbol

On running create schematic symbol we get CMD_LOG file, .sym and .spl files.

CMD_LOG File

It contains series of commands obtained while running each step. For example: -lib work /home/ise/ISE/full_adder/adder.v The "-lib" option is used in Xilinx ISE to specify the target library for the design files. In the command "-lib work /home/ise/ISE/full_adder/adder.v", the target library is specified as "work", which is a default library in the ISE tool suite. The "/home/ise/ISE/full_adder/adder.v" part of the command is the path and filename of the design file that will be added to the target library. The library can be checked by right clicking on verilog file and selecting source properties

SPL File

It is a configuration file or template for an electronic circuit design, potentially in Verilog or another hardware description language. For a full adder, the following configurations are included in .spl file:

SYM File

A .sym file is a file format used in electronic design automation (EDA) software to store schematic symbols. Schematic symbols are graphical representations of electronic components or devices, used to represent them in a schematic diagram. It contains following details:

"pin": This specifies that the XML element represents a pin. "polarity": This specifies whether the pin is an input or output. "x" and "y": These specify the coordinates of the pin on the schematic diagram. Similarly the specifications of orientation and font details are provided for textual content. When opened in symbol editor, schematic symbol of full adder can be viewed.

View command line log file

It is used to view all the commands that are being executed during each step. It opens CMD_LOG file in ISE tool to be directly viewed.

View HDL instantiation template

On running we can view instantiation of the verilog code as .tfi file.

TFI File

A TFI (Text Format Instantiation) file is a text file that contains instantiations of different components used in a digital design. The code provided in .tfi file is:

If we are using a vhdl file then a vhdl instantiation is provided that is represented as a .vhi file