Challenge1_Counters - muneeb-mbytes/FPGABoard_edgeSpartan6 GitHub Wiki
Solution:
Click this for code files for 00 to 99 counter
oneHz_gen:
1Hz is generated from a 50MHz clock by making use of a counter, ctr_reg which counts till 25,000,000 and then it toggles a new clock signal to obtain a clock signal of frequency 1Hz. The formula used to obtain the counter value is (50MHz / 1Hz / 2). ctr_reg is declared as 26 bit register to hold the given value. This register value can be obtained by taking log to the base 2 of counter value which comes up to be 25(one extra bit just to be careful).
debouncer
The input push buttons, start, stop, load and reset are passed through the debouncer circuit code.
statedetect
Start and stop push buttons need to hold their values after being pressed once. To achieve this we make use of state detect code, where we define states to start and stop. "result_start" is assigned a state of 0 and "result_stop" is assigned a state of 1.
digits
The digits.v code contains the main logic. In this code we specify output of oneHz_gen, "clk_1Hz" output of debouncer circuit code, "result_load" and "result_reset", and outputs of statedetect code, "state" as inputs performing load, reset, start and stop actions respectively. We also specify updown slide switch for mode control. During the up mode, the counter counts from 0 to 99 and during the down mode, the counter counts from 99 to 00. When reset is pressed the count goes 99 in down mode and the count goes to 0 in up mode. When load is pressed the count goes to 90 in up mode and the count goes to 10 in down mode. During the roll over the buzzer rings for 1 second. Reset is made asynchronous.
bintobcd:
The output of the counter is stored as an 8 bit register, this needs to be converted to an 8 bit BCD for displaying on a seven segment display. To achieve this we make use of Double dabble algorithm. Thus the 8 bit count value holding binary number is passed to bintobcd code and we obtain eight bit bcd number. For more information about double dabble algorithm refer:
seg7control:
This file contains the logic for controlling digit select and digit timer. Digit select is a 2
bit counter for selecting each of 4 digits. Digit timer is a counter for digit refresh. For
each of the four digits to appear bright and continuously illuminated, all four digits
should be driven once every 1 to 16ms. So we have a refresh period of 4ms within
the range and each digit must be ON for 1/4 period of the refresh period I.e,. each
digit must be ON for 1ms.
Thus counter for digit refresh will be 50,000. This is calculated as (20ns x
counter)=1ms. 20ns is the period of 50MHz clock. Thus based on when the digit
timer reaches this value, the digit select is incremented by 1 to select the next digit. The value “ones” is displayed on first seven segment display, “tens” is displayed on
the second display whereas on third and fourth seven segment displays a dash is
displayed by activating the “g” segment
top:
It is the top level module that instantiates all the modules.
VIDEO
0000 to 9999 Counter
We can even do the same for 4 bit counter, to count from 0000 to 9999 with the similar approach by making few modifications in digits.v, bintobcd.v and seg7control.v. Click this for code files for 0000 to 9999 counter