BCD Seven Segment Display and Full adder - muneeb-mbytes/FPGABoard_edgeSpartan6 GitHub Wiki
BCD to Seven segment :
A BCD (Binary Coded Decimal) to Seven-Segment Decoder is a digital circuit that converts a 4-bit BCD code into the seven-segment display code that can be used to display numbers on a seven-segment display.
It consists of seven LED segments arranged in the shape of the number "8", with an additional LED segment for displaying a decimal point.
The seven segments are labeled as A, B, C, D, E, F, and G.
The EDGE Board consist of 4 digit 7 segment displays with common anode. Each of the seven segment contains LEDs can be turned on by sending active low signal.
For example, to display digit 8 in the seven segments display. All the segments are enabled using active low ‘0’ signal.
Block Diagram:
For Common Anode:
Verilog Code for BCD Seven Segment Display using Common Anode Logic
module sevensmt(bcd,digit,seg);
input [3:0] bcd;
input [3:0] digit; //enable signal to 4 digit seven segment display
output reg[7:0] seg;
assign digit = 4'b1111;
always @ (bcd)
begin
case(bcd)
4'b0000: seg = 8'b00000011; //displays 0
4'b0001: seg = 8'b10011111; //displays 1
4'b0010: seg = 8'b00100101; //displays 2
4'b0011: seg = 8'b00001101; //displays 3
4'b0100: seg = 8'b10011001; //displays 4
4'b0101: seg = 8'b01001001; //displays 5
4'b0110: seg = 8'b01000001; //displays 6
4'b0111: seg = 8'b00011111; //displays 7
4'b1000: seg = 8'b00000001; //displays 8
4'b1001: seg = 8'b00001001; //displays 9
4'b1010: seg = 8'b11011011; //for other cases c and f led's are turned on
4'b1011: seg = 8'b11011011;
4'b1100: seg = 8'b11011011;
4'b1101: seg = 8'b11011011;
4'b1110: seg = 8'b11011011;
4'b1111: seg = 8'b11011011;
endcase
end
endmodule
UCF (user constrained file)
NET "BCDin[0]" LOC = P22; // slide switches
NET "BCDin[1]" LOC = P21;
NET "BCDin[2]" LOC = P17;
NET "BCDin[3]" LOC = P16;
NET "digit[0]" LOC = P127; //enable signals
NET "digit[1]" LOC = P131;
NET "digit[2]" LOC = P132;
NET "digit[3]" LOC = P133;
NET "Seven_Segment[0]" LOC = P134; //seven segment display led
NET "Seven_Segment[1]" LOC = P137;
NET "Seven_Segment[2]" LOC = P138;
NET "Seven_Segment[3]" LOC = P139;
NET "Seven_Segment[4]" LOC = P140;
NET "Seven_Segment[5]" LOC = P141;
NET "Seven_Segment[6]" LOC = P142;
NET "Seven_Segment[7]" LOC = P143;
Seven Segment Display video
Full Adder
Full Adder has 3 inputs a,b,c and 2 outputs sum,carry.
Block diagram:
Truth Table
Equation
sum=a⊕b⊕c;
carry=ab+bc+ca
Verilog code for Full adder;
In the below code, we are using dataflow modelling because, in a dataflow model, the number of lines of code is less when compared with behavioural modelling and gate level modelling.
module full_adder(a,b,c,sum,carry);
input a,b,c; //inputs
output sum; //output
output carry ; // output
assign sum=a^b^c;
assign carry=a&b|b&c|a&c;
endmodule
UCF Pins:
NET "a" LOC=P22; //connected to switch
NET "b" LOC=P21;//connected to switch
NET "c" LOC=P17;//connected to switch
NET "sum" LOC=P33;//connected to led
NET "carry " LOC=P32;//connected to led