Audio, SPI ADC and SPI DAC - muneeb-mbytes/FPGABoard_edgeSpartan6 GitHub Wiki

Audio

audio drawio

Consists of 2 Pins:

1. NET "AUDIO_L" LOC = "p79";

  • This sentence is defining a net named "AUDIO_L" and assigning it to the physical pin "p79".

  • "AUDIO_L" is typically the left audio channel signal, which is used to transmit audio signals for the left speaker or earphone.

2. NET "AUDIO_R" LOC = "p78";

  • This sentence is defining a net named "AUDIO_R" and assigning it to the physical pin "p78".

  • "AUDIO_R" is typically the right audio channel signal, which is used to transmit audio signals for the right speaker or earphone.

SPI ADC (Serial Peripheral Interface Analog to Digital Converter)

adctemp drawio

Consists of 4 Pins:

1. NET "cs" LOC = "p118" ;

  • This line defines a signal named "cs" that is connected to pin "p118" on the FPGA board.

  • "cs" is the chip select signal which is used to enable or disable the ADC for communication.

2. NET "din" LOC = "p119" ;

  • This line defines a signal named "din" that is connected to pin "p119" on the FPGA board.

  • "din" is the data input signal that carries data from the FPGA to the ADC.

3. NET "do" LOC = "P120";

  • This line defines a signal named "do" that is connected to pin "P120" on the FPGA board.

  • "do" is the data output signal that carries data from the ADC to the FPGA.

4. NET "sck" LOC = "p121" ;

  • This line defines a signal named "sck" that is connected to pin "p121" on the FPGA board.

  • "sck" is the clock signal that synchronizes data transfer between the FPGA and the ADC.

  • Light Detect Resistor LDR is connected at the ADC channel Ch6. LDR provides variable resistance based on the light intensity that falls upon it.

  • Temperature Sensor LM35 is connected at the ADC channel Ch7.

SPI DAC (Serial Peripheral Interface Digital to Analog Converter)

dac drawio

Consists of 3 Pins:

1. NET "CS" LOC = P123;

  • This line connects the "Chip Select" (CS) pin of the SPI DAC to pin P123 of the FPGA board.

  • This pin is typically used to enable or disable communication with the DAC.

2. NET "MOSI" LOC = P124;

  • This line connects the "Master Output, Slave Input" (MOSI) pin of the SPI DAC to pin P124 of the FPGA board.

  • This pin is used to transmit data from the FPGA board to the DAC.

3. NET "SCK" LOC = P126;

  • This line connects the "Serial Clock" (SCK) pin of the SPI DAC to pin P126 of the FPGA board.

  • This pin provides the clock signal used to synchronize data transmission between the FPGA board and the DAC.