The H3 CPU has three Pulse Width Modulation output signals:

Name	PIN	Function2	Func3	Comment
S_PWM	PL10	S_PWM	None	connected to PWR-LED
PWM0	PA5	UART0_RX	PWM0	Exposed at UART (Debug) J3 pin2
PWM1	PA6	SIM_PREN	PWM1	Exposted at connector pin 7

The PWM divider divides the clock (24MHz) by 1~4096 according to the PWM register values.

https://github.com/armbian/sunxi-DT-overlays/blob/master/sun8i-h3/README.sun8i-h3-overlays

overlays=pwm

Activates hardware PWM controller

PWM pin: PA5

Pin PA5 is used as UART0 RX by default, so if this overlay is activated, UART0 and kernel console on ttyS0 will be disabled

demonstrator@orangepizero:~$ ls /sys/class/pwm/pwmchip0
device  export  npwm  power  subsystem  uevent  unexport
demonstrator@orangepizero:/sys/class/pwm/pwmchip0$ cat npwm
1
demonstrator@orangepizero:/sys/class/pwm/pwmchip0$ ls pwm0/
capture  duty_cycle  enable  period  polarity  power  uevent
demonstrator@orangepizero:/sys/class/pwm/pwmchip0$ cat  pwm0/duty_cycle
0
demonstrator@orangepizero:/sys/class/pwm/pwmchip0$ cat  pwm0/period
168
demonstrator@orangepizero:/sys/class/pwm/pwmchip0$ cat  pwm0/polarity
inversed
demonstrator@orangepizero:/sys/class/pwm/pwmchip0$ cat  pwm0/capture
cat: pwm0/capture: Function not implemented
demonstrator@orangepizero:/sys/class/pwm/pwmchip0$

• https://github.com/iboguslavsky/pwm-sunxi-opi0