//
// 8-bit Shift-Left Register with Positive-Edge Clock,
// Serial In, and Serial Out
//
module v_shift_registers_1 (C, SI, SO);
  input C,SI;
  output SO;
  reg [7:0] tmp;

  always @(posedge C) begin
    tmp = {tmp[6:0], SI};
  end
  assign SO = tmp[7];
endmodule

//
// 3-Bit 1-of-9 Priority Encoder
//
(* priority_extract="force" *)
module v_priority_encoder_1 (sel, code);
  input [7:0] sel;
  output [2:0] code;
  reg [2:0] code;
  always @(sel) begin
    if (sel[0]) code = 3'b000;
    else if (sel[1]) code = 3'b001;
    else if (sel[2]) code = 3'b010;
    else if (sel[3]) code = 3'b011;
    else if (sel[4]) code = 3'b100;
    else if (sel[5]) code = 3'b101;
    else if (sel[6]) code = 3'b110;
    else if (sel[7]) code = 3'b111;
    else code = 3'bxxx;
  end
endmodule

module v_logical_shifters_1 (DI, SEL, SO);
  input [7:0] DI;
  input [1:0] SEL;
  output [7:0] SO;
  reg [7:0] SO;
  always @(DI or SEL) begin
    case (SEL)
    2'b00 : SO = DI;
    2'b01 : SO = DI << 1;
    2'b10 : SO = DI << 2;
    default : SO = DI << 3;
    endcase
  end
endmodule