soc design - modrpc/info GitHub Wiki
- http://www.deepchip.com
- SNUG: https://snug.search.synopsys.com/
- Jason Andrews: ARM Coverification: https://github.com/modrpc/info/blob/master/docsDigital%20Systems/SOC-ARM-SOC-Coverification.pdf
-
JTAG-based
- JTAG is about writing/reading registers in CPU.
- What can we not do when we can write to registers and control CPU
- Stub-based
- System (CPU) initialization code
- e.g. configure operating modes, caches, memory protection, MMU unit, interrupt controller configuration, timer setup, DRAM initialization
- HAL (Hardware Abstraction Layer)
- On top of system initialization code, provides common interface for higher-level software to use hardware-specific functionality after the system is initialized
- Hardware diagnostics suite
- RTOS
- RTOS device drivers
- Applications
- Wiki: https://en.wikipedia.org/wiki/Computer_architecture_simulator
- aka: architectural simulator
- architecture simulator which simulates an electronic system at such a level of detail that complete software stacks from real systems (i.e. OS, device drivers, user applications) can run on the simulator without any modification
- includes:
- processor cores
- peripheral devices
- memories
- interconnection buses
- network connections
- only simulates instruction set architecture usually faster but not cycle-accruate to a specific implementation of this architecture
- wiki: https://en.wikipedia.org/wiki/Instruction_set_simulator
- faster than cycle-accurate simulator
- useful when the processor core itself is not being verified
- OVP (Open Virtual Platforms)
- computer program that simulates a microarchitecture on a cycle-by-cycle basis.
- c.f. instruction-set simulator
- use when time precisons are very important from legacy reasons.
- ensures that all operations (incl. branch prediction, cache misses, fetches, pipeline stalls, thread context switching) are executed in proper virtual time
- Benefits
- Allows to start SW development months before RTL/FPGA prototypes are available
- Creates a first-working virtual prototype in days vs weeks
- SW adaptor which enables user applications and OS drivers to establish a virtual protocol connection to PZ1. (CDNS)
- emulates HW design along with SW applications via OS drivers
- run SW application against emulated HW via OS drivers
- perform SW OS driver verification
- consists of
- transactor that enables high-speed transactions between DUT (in PZ1) and host workstation
- user-app => OS driver => transactor ====> BFM => DUT
- user-app running on any OS supported by VM (virtual machine)
- transactor that enables high-speed transactions between DUT (in PZ1) and host workstation
- Benefits
- 60X speedup of OS boot over in-circuit emulation for pre-silicon software validation; 10X speedup for post-boot software execution
- integrates
- high-performance transaction-level model of the CPU subsystem running on the Virtual Platform (VSP)
- RTL for the rest of the SOC on PZ1
- SNPS
-
Embedded.com: Virtual Prototyping
-
ARM-based Android hardware-software design using virtual prototypes (mostly SNPS virtualizer)
- Pt.1: Why virtualize
- Pt.2: Building a sensor subsystem
- Pt.3: Integrating Android's HAL
-
ARM-based Android hardware-software design using virtual prototypes (mostly SNPS virtualizer)
- Architecture: https://source.android.com/devices/architecture/
- ARM: https://en.wikipedia.org/wiki/ARM_architecture
- ARM Cotext-A53: https://en.wikipedia.org/wiki/ARM_Cortex-A53
- Alternative:
- Cadence Interconnect Validator
- MIPI Alliance: https://www.mipi.org
- MIPI Specifications: https://www.mipi.org/specifications
- Cadence VIP
- Synopsys DesignWare MIPI
- CSI-2 (Cameria Serial Interface 2) https://www.mipi.org/specifications/csi-2
- DSI-2 (Display Serial Interface 2) https://www.mipi.org/specifications/dsi-2
- C-PHY (physical layer for cameras) https://www.mipi.org/specifications/c-phy
- D-PHY (physical layer for displays) https://www.mipi.org/specifications/d-phy
- M-PHY (physical layer for multimedia and chip-to-chip IPC) https://www.mipi.org/specifications/d-phy