embedded systems - modrpc/info GitHub Wiki

Table of Contents

Overview

Software Layer

BIOS vs BSP vs Firmware

  • Firmware is equivalent to "software" in PC world. Unlike PC's, user can't load whatever he/she wants on the embedded board. So software on an embedded system is "firm", this is why software called as firmware in embedded world.
  • BSP (Board Support Package) is a bunch of patches/modifications to adopt a sw system (usually O.S. like winCE, linux) to your custom board. i.e. you have a board with T.I.'s Omap processor, linux kernel already have Omap support, but you need to tailor it for your board. You have different display, different keypad etc. All these changes constitues the BSP.
  • BIOS (Basic Input Output System), orginally a PC thing. It's the first piece of program runs when the computer powered up and responsible for basic HW configuration and bootloading. I've heard some terms like DSP BIOS, but normally BIOS means just PC BIOS to me.

Firmware

  • See "ARM System Development Guide" Chapter 10. Firmware

Firmware Execution Flow

  • set up target platform:
    • program the hardware system registers
    • platform identification
    • diagnostics
    • debug interface
    • command line interpreter
  • abstract the hardware
    • HAL (hardware abstraction layer)
    • device driver
  • load a bootable image
    • basic filing system
  • relinquish control
    • alter the PC to point into the new image

Memory

Memory Controllers

  • Overview
  • Memory Mapping:
    • maps: memory address => (bank, row, column)
  • Arbiter:
    • chooses the order in which requests access memory
  • Command Generator:

Communication

Interconnection schemes

Buses

Shared memories

FIFO queues

Simple wires (point-to-point connections)

On-chip networks

I/O: Interfacing

Bus and Protocol

  • BUS: set of wires for communication
    • addr: destination
    • data: payload
    • wr/rd, enable: control (e.g. "enable" need to show "NONE vs wr/rd")
  • PROTOCOL: rules how wires are used for communication
    • described by timing diagram
    • protocol consists of subprotocols
      • e.g. memory read protocol, memory write protocol
      • subprotocol isknown as transaction or bus cycle (which consists of multiple clcock cycles)

Basic Protocol Concetps

  • Actors: master and slave
    • Master initiates transfer
    • Slave responds to master
  • Data direction between actors:
    • who sends data
    • master can be either a sender (push) or receiver (pull)
  • Address: where data should go to or come from
    • e.g. memory addresss, which device, which register in a particular device
  • Time multiplexing: sharing
    • share the wires for multiple data items
    • e.g. send 16 bits over 8-bit bus
  • Control methods: schemes for initiating/ending transfer
    • strobe protocol: timing-constraints
     +---------+                   +---------+
     |  master |       req         |  slave  |
     |         +------------------>+         |
     |         |                   |         |
     |         +<------------------+         |
     |         |       data        |         |
     +---------+                   +---------+
    • handshake protocol:
     +---------+                   +---------+
     |  master |       req         |  slave  |
     |         +------------------>+         |
     |         |                   |         |
     |         +<------------------+         |
     |         |       ack         |         |
     |         +<------------------+         |
     |         |       data        |         |
     +---------+                   +---------+
    • hybrid protocol:
     +---------+                   +---------+
     |  master |       req         |  slave  |
     |         +------------------>+         |
     |         |                   |         |
     |         +<------------------+         |
     |         |       wait        |         |
     |         +<------------------+         |
     |         |       data        |         |
     +---------+                   +---------+

Synchronous vs Asynchrnous Bus

Synchronous Bus

  • One control line carries clock signal
  • Example: SPI, Memory bus -- addresss/read command on the first clock cycle, data appears on the fifth clock
  • (+) Easy to implement protocol in a small FSM -- small interface logic
  • (+) Bus if fast
  • (-) Every device on the bus must run at the same clock rate
  • (-) Due to clock skew problems, syncronous buses cannot be long if they are fast

Asynchronous Bus

I/O Addressing (i.e. Designating Destination) Methods

Port-based I/O

  • a.k.a. Parallel I/O
    • port can be directly read/written by instructions just like reading/writing any registers

Bus-based I/O

  • processor has a set of ports (addr, data, control) and uses such ports to access memory as well as peripherals
  • processor implements bus protocol in the processor
  • two methods for a processor to communicate with peripherals
    • memory-mapped I/O
    • standard I/O (I/O-mapped I/O)

Memory-Mapped I/O

  • peripherals (actually, I/O registersoccupy specific addresses in the existing address space
  • e.g. given 16-bit address bus, lower 32K correspond to memory address and upper 32K correspond to I/O addresses
  • (+) don't need special instruction for I/O access -- MOV, ADD over memory location will suffice
  • (-) loss of memory address space

Standard I/O (I/O-mapped I/O)

  • bus includes a special pin, M/IO to indicate whether the bus access is to memory or to a peripheral
  • (-) special I/O instruction needed -- e.g. INP, OUTP

DMA

DMA Transfer Types

  • flyby DMA transfer: single-cycle, single-address
    • single bus operation used to accomplish transfer; data read from the source, written to the destination simultaneously
  • fetch-and-deposit DMA transfer: dual-cycle, dual-address, flow-through
    • 1st cycle (I/O read): data read from I/O device into DMA controller's temporary data register
    • 2nd cycle (I/O read): data read from DMA controller's temporary data register to memory

DMA Transfer Modes

  • single transfer mode: one data value for each DMA request assertion (slowest)
  • block transfer mode: multiple DMA transfers when DMA controller has gained the bus (from CPU)
    • DMA controller performs entire DMA sequence
  • demand transfer mode: multiple DMA transfers when DMA controller has gained the bus (from CPU)

Protocols

I2C

SPI

Basics

  • SPI connection
  • SPI master port 0 registers
    • SPI0CS: control register
    • SPI0FIFO: written to transmit a byte and read to get the byte received back
    • SPI0CLK: configures the SPI clock frequency by dividing the 250Mhz peripheral clock by a power of two specified in the register. e.g. when SPI0CLK=2, clock frequency = 250Mhz/2 = 125Mhz.

Example: Connect RPI master with FPGA slave over SPI

RPI Linux code: device driver on top of EasyPIO

void spi_init(int freq, int settings) {
     pin_mode(8, ALT0);   // CE0b
     pin_mode(9, ALT0);   // MISO
     pin_mode(10, ALT0);  // MOSI
     pin_mode(11, ALT0);  // SCLK
     SPI0CLK = 250000000/freq;
     SPI0CS = settings;
     SPICSbits.TA = 1; // turn SPI on
}

char spi_sendrecv(char data) {
     SPI0FIFO = send;
     while (!SPI0CSbits.DONE) ;
     return SPI0FIFO;
}

FPGA side: SPI slave controller

module spi_slave(input logic sck,       // From master
                 input logic mosi,      // From master
                 output logic miso,     // To master
                 input logic reset,     // System reset
                 input logic [7:0] d,   // Data to send
                 output logic [7:0] q); // Data received
  logic [2:0] cnt;
  logic qdelayed;
  // 3-bit counter tracks when full byte is transmitted
  always_ff @(negedge sck, posedge reset)
    if (reset) cnt = 0;
    else cnt = cnt + 3’b1;

  // Loadable shift register
  // Loads d at the start, shifts mosi into bottom on each step
  always_ff @(posedge sck)
    q < = (cnt == 0) ? {d[6:0], mosi} : {q[6:0], mosi};

  // Align miso to falling edge of sck
  // Load d at the start
  always_ff @(negedge sck)
    qdelayed = q[7];

  assign miso = (count == 0) ? d[7] : qdelayed;
endmodule


module spi_slave_receive_only(input logic sck,       // From master
                              input logic mosi,      // From master
                              output logic [7:0] q); // Data received
  always_ff @(posedge sck)
    q < = {q[6:0], sdi}; // shift register
endmodule

UART

Basics

Example: Connect RPI with FPGA with UART

RPI Linux code: device driver on top of EasyPIO

void uart_init(int baud) {
  uint fb = 12000000/baud;      // 3 MHz UART clock
  pinMode(14, ALT0);            // TX
  pinMode(15, ALT0);            // RX
  UART_IBRD = fb >> 6;          // 6 Fract, 16 Int bits of BRD
  UART_FBRD = fb & 63;
  UART_LCRHbits.WLEN = 3;       // 8 Data, 1 Stop, no Parity, no FIFO, no Flow
  UART_CRbits.UARTEN = 1;       // Enable uart
}

char getchar_serial(void) {
  while (UART_FRbits.RXFE);     // Wait until data is available
  return UART_DRbits.DATA;      // Return char from serial port
}
void putchar_serial(char c) {
  while (!UART_FRbits.TXFE);    // Wait until ready to transmit
  UART_DRbits.DATA = c;         // Send char to serial port
}

#define MAX_STR_LEN 80
void getstr_serial(char *str) {
  int i = 0;
  do {                          // Read an entire string until
    str[i] = getchar_serial();  // Carriage return
  } while ((str[i++ ] ! = '\r')
          && (i < MAX_STR_LEN));// Look for carriage return
  str[i-1] = 0;                 // Null-terminate the string
}
void putstr_serial(char *str) {
  int i = 0;
  while (str[i] ! = 0) {        // Iterate over string
    putchar_serial(str[i++ ]);    // Send each character
  }
}

FPGA side: Serial RX/TX controller

module serial_rx(); ... endmodule
module serial_tx(); ... endmodule

Timers

Character LCDs

VGA Monitor

Basics

  • VGA standard: 640x480 resolution; introduced in 1987 for IBM PS/2

Motors

PCIe

Basics

  • No bus arbitration needed
  • PCIe communication performed in packets (dest + payload):
    • This means "not time-multiplexed" (e.g. bus arbitrated)
  • These days, video displays are connected through PCIe

USB

Infiniband

JTAG

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