Moore machines (output dependent only on states) require more states but safer
Specifying FSM's transition behavior
STEP #1: Declare two states
state: current state
next_state: F(state, inputs) computed in combinational logic; will be updated on the next rising edge
STEP #2: Create state F/F
Create physical means of transitioing from curr_state to the next state
always @(posedge clk) beginif (rst) state <= init_state;
else state <= next_state;
end
STEP #3: Compute next state
Implement conditional-transitioning mechanism thta will choose what the next state should be and under what conditions a transition should be made
Create always @* (combinational) process which will compute next_state
always @*begin// to avoid latch inference over next_state, assign default value first// - this also allows to save code (no full if-else blocks)
next_state = state;
case (state)
s0: ...
s1: ...
default: next_state = initial_state;
endcaseend
STEP #4: Outputs
Output values based on current state, either in contasgn or combo logic
"Decouple" producer and consumer (which is not synchronized for many reasons)
Usages:
Interfacing I/O devices (e.g. network interface): data bursts from network, then processor bursts to memory buffer (or reads one word at a time from interface). Operations not synchronized
receive data from a high speed serial interface
buffer data for transmitting UART to host (e.g. RTL generates faster than host can receive at 9600 baud)
align data in time for math operations
buffer data to/from SDRAM interface
crossing the clock domains: two clocks -- one for read, the other for write