Up to now the cores have only be compiled under Linux. This page thus only describes the necessary Linux setup. The same instructions probably also work under Windows since the same tools being used are available for Windows as well.

Prerequisites

The cores are written in a combination of Verilog and VHDL. A synthesis tool is required to compile this into a binary FPGA configuration (/sof/rbf). Since the FPGA on the MiST is a member of the Altera Cyclone III family, the Altera Quartus II suite is required. The free Web Edition is sufficient. See e.g.

• http://dl.altera.com/13.1/?edition=web
• https://www.intel.com/content/www/us/en/software-kit/666220/intel-quartus-ii-web-edition-design-software-version-13-1-for-linux.html

(the latest version supporting Cyclone III is 13.1).

There's also a Dockerized Quartus 13.1 for new distros where this old Quartus version doesn't run flawlessly.

Compiling

The core source code is available from the MiST source repository.

To load the project simple open the project file (.qpf, e.g. core/mist/mist.qpf) in Quartus. On the left side under "Flow" select "Compilation". and double click "Compile Design". Depending in the speed of your computer this may take from some minutes up to an hour.**

Running the core

Two files are generated in the out directory during compilation:

• mist.sof is a "SRAM Object File". This can be uploaded to the FPGA using a Byte Blaster JTAG cable or similar
• mist.rbf is a raw binary file. This can be uploaded to the FPGA from SD card using the MISTs on-board IO controller

Running from SD card

To allow for auto configuration the raw binary file of the default core needs to be renamed to core.rbf and placed in the root directory of the SD card. The IO controller will find it at system initialization and upload it to the FPGA. This works exactly as if a normal user would run cores.

Running via USB Blaster cable

The usage of a USB byte blaster cable is explained on a separate page.