sdk例程： ps_qspi_flash读写例程 - minichao9901/TangNano-20k-Zynq-7020 GitHub Wiki
从串口接收文件或者图片，然后存入qspi_flash，然后读出，然后校验比对
#ifndef QSPI_FLASH_H_
#define QSPI_FLASH_H_
#include "COMMON.h"
#include "xqspips.h"
typedef struct{
u8 wr_buff[1024*1024];
u8 rd_buff[1024*1024];
u32 wr_length;
u32 rd_length;
u32 flash_start_addr;
u8 wr_en;
u8 rd_en;
} qspi_buff_t;
extern XQspiPs QspiInstance;
void FlashErase(XQspiPs *QspiPtr, u32 Address, u32 ByteCount);
void FlashWrite(XQspiPs *QspiPtr, u32 Address, u8* pBuff, u32 ByteCount, u8 Command);
void FlashRead(XQspiPs *QspiPtr, u32 Address, u8* pBuff, u32 ByteCount, u8 Command);
int FlashReadID(void);
void FlashQuadEnable(XQspiPs *QspiPtr);
void QspiFlash_Init(void);
int QspiFlash_Write_Read_Demo(qspi_buff_t *pbuff);
void QspiFlash_Read_Demo(qspi_buff_t *pbuff);
#endif /* QSPI_FLASH_H_ */#include "xqspips.h" /* QSPI device driver */
#include "QspiFlash.h"
#define WRITE_STATUS_CMD 0x01
#define WRITE_CMD 0x02
#define READ_CMD 0x03
#define WRITE_DISABLE_CMD 0x04
#define READ_STATUS_CMD 0x05
#define WRITE_ENABLE_CMD 0x06
#define FAST_READ_CMD 0x0B
#define DUAL_READ_CMD 0x3B
#define QUAD_READ_CMD 0x6B
#define BULK_ERASE_CMD 0xC7
#define SEC_ERASE_CMD 0x20 /*xilinx demo程序有错误，进行了修改*/
#define READ_ID 0x9F
#define COMMAND_OFFSET 0 /* FLASH instruction */
#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */
#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */
#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */
#define DATA_OFFSET 4 /* Start of Data for Read/Write */
#define DUMMY_OFFSET 4 /* Dummy byte offset for fast, dual and quad
* reads
*/
#define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and
* quad reads
*/
#define RD_ID_SIZE 4 /* Read ID command + 3 bytes ID response */
#define BULK_ERASE_SIZE 1 /* Bulk Erase command size */
#define SEC_ERASE_SIZE 4 /* Sector Erase command + Sector address */
/*
* The following constants specify the extra bytes which are sent to the
* FLASH on the QSPI interface, that are not data, but control information
* which includes the command and address
*/
#define OVERHEAD_SIZE 4
/*
* The following constants specify the page size, sector size, and number of
* pages and sectors for the FLASH. The page size specifies a max number of
* bytes that can be written to the FLASH with a single transfer.
*/
/*xilinx demo程序有错误，进行了修改*/
#define PAGE_SIZE 256
#define NUM_PAGES 16384
#define SECTOR_SIZE 4096
#define NUM_SECTORS 1024
/* Flash address to which data is ot be written.*/
#define TEST_ADDRESS 0x00400000 /*4Mbyte*/
/*
* The following constants specify the max amount of data and the size of the
* the buffer required to hold the data and overhead to transfer the data to
* and from the FLASH.
*/
#define MAX_DATA (1024 * PAGE_SIZE)
/****************************************************************************************/
#define QSPI_DEVICE_ID XPAR_XQSPIPS_0_DEVICE_ID
XQspiPs QspiInstance;
static u8 ReadBuffer[MAX_DATA + DATA_OFFSET + DUMMY_SIZE];
static u8 WriteBuffer[PAGE_SIZE + DATA_OFFSET];
void FlashWrite(XQspiPs *QspiPtr, u32 Address, u8* pBuff, u32 ByteCount,
u8 Command) {
u8 WriteEnableCmd = { WRITE_ENABLE_CMD };
u8 ReadStatusCmd[] = { READ_STATUS_CMD, 0 }; /* must send 2 bytes */
u8 FlashStatus[2];
/*
* Send the write enable command to the FLASH so that it can be
* written to, this needs to be sent as a seperate transfer before
* the write
*/
XQspiPs_PolledTransfer(QspiPtr, &WriteEnableCmd, NULL,
sizeof(WriteEnableCmd));
/*
* Setup the write command with the specified address and data for the
* FLASH
*/
WriteBuffer[COMMAND_OFFSET] = Command;
WriteBuffer[ADDRESS_1_OFFSET] = (u8) ((Address & 0xFF0000) >> 16);
WriteBuffer[ADDRESS_2_OFFSET] = (u8) ((Address & 0xFF00) >> 8);
WriteBuffer[ADDRESS_3_OFFSET] = (u8) (Address & 0xFF);
memcpy(&WriteBuffer[4], pBuff, ByteCount);
/*
* Send the write command, address, and data to the FLASH to be
* written, no receive buffer is specified since there is nothing to
* receive
*/
XQspiPs_PolledTransfer(QspiPtr, WriteBuffer, NULL,
ByteCount + OVERHEAD_SIZE);
/*
* Wait for the write command to the FLASH to be completed, it takes
* some time for the data to be written
*/
while (1) {
/*
* Poll the status register of the FLASH to determine when it
* completes, by sending a read status command and receiving the
* status byte
*/
XQspiPs_PolledTransfer(QspiPtr, ReadStatusCmd, FlashStatus,
sizeof(ReadStatusCmd));
/*
* If the status indicates the write is done, then stop waiting,
* if a value of 0xFF in the status byte is read from the
* device and this loop never exits, the device slave select is
* possibly incorrect such that the device status is not being
* read
*/
if ((FlashStatus[1] & 0x01) == 0) {
break;
}
}
}
void FlashRead(XQspiPs *QspiPtr, u32 Address, u8* pBuff, u32 ByteCount, u8 Command) {
/*
* Setup the write command with the specified address and data for the
* FLASH
*/
WriteBuffer[COMMAND_OFFSET] = Command;
WriteBuffer[ADDRESS_1_OFFSET] = (u8) ((Address & 0xFF0000) >> 16);
WriteBuffer[ADDRESS_2_OFFSET] = (u8) ((Address & 0xFF00) >> 8);
WriteBuffer[ADDRESS_3_OFFSET] = (u8) (Address & 0xFF);
if ((Command == FAST_READ_CMD) || (Command == DUAL_READ_CMD)
|| (Command == QUAD_READ_CMD)) {
ByteCount += DUMMY_SIZE;
}
/*
* Send the read command to the FLASH to read the specified number
* of bytes from the FLASH, send the read command and address and
* receive the specified number of bytes of data in the data buffer
*/
XQspiPs_PolledTransfer(QspiPtr, WriteBuffer, pBuff,
ByteCount + OVERHEAD_SIZE);
}
void FlashErase(XQspiPs *QspiPtr, u32 Address, u32 ByteCount) {
u8 WriteEnableCmd = { WRITE_ENABLE_CMD };
u8 ReadStatusCmd[] = { READ_STATUS_CMD, 0 }; /* must send 2 bytes */
u8 FlashStatus[2];
int Sector;
/*
* If erase size is same as the total size of the flash, use bulk erase
* command
*/
if (ByteCount == (NUM_SECTORS * SECTOR_SIZE)) {
/*
* Send the write enable command to the FLASH so that it can be
* written to, this needs to be sent as a seperate transfer
* before the erase
*/
XQspiPs_PolledTransfer(QspiPtr, &WriteEnableCmd, NULL,
sizeof(WriteEnableCmd));
/* Setup the bulk erase command*/
WriteBuffer[COMMAND_OFFSET] = BULK_ERASE_CMD;
/*
* Send the bulk erase command; no receive buffer is specified
* since there is nothing to receive
*/
XQspiPs_PolledTransfer(QspiPtr, WriteBuffer, NULL,
BULK_ERASE_SIZE);
/* Wait for the erase command to the FLASH to be completed*/
while (1) {
/*
* Poll the status register of the device to determine
* when it completes, by sending a read status command
* and receiving the status byte
*/
XQspiPs_PolledTransfer(QspiPtr, ReadStatusCmd, FlashStatus,
sizeof(ReadStatusCmd));
/*
* If the status indicates the write is done, then stop
* waiting; if a value of 0xFF in the status byte is
* read from the device and this loop never exits, the
* device slave select is possibly incorrect such that
* the device status is not being read
*/
if ((FlashStatus[1] & 0x01) == 0) {
break;
}
}
return;
}
/*
* If the erase size is less than the total size of the flash, use
* sector erase command
*/
for (Sector = 0; Sector < ((ByteCount / SECTOR_SIZE) + 1); Sector++) {
/*
* Send the write enable command to the SEEPOM so that it can be
* written to, this needs to be sent as a seperate transfer
* before the write
*/
XQspiPs_PolledTransfer(QspiPtr, &WriteEnableCmd, NULL,
sizeof(WriteEnableCmd));
/*
* Setup the write command with the specified address and data
* for the FLASH
*/
WriteBuffer[COMMAND_OFFSET] = SEC_ERASE_CMD;
WriteBuffer[ADDRESS_1_OFFSET] = (u8) (Address >> 16);
WriteBuffer[ADDRESS_2_OFFSET] = (u8) (Address >> 8);
WriteBuffer[ADDRESS_3_OFFSET] = (u8) (Address & 0xFF);
/*
* Send the sector erase command and address; no receive buffer
* is specified since there is nothing to receive
*/
XQspiPs_PolledTransfer(QspiPtr, WriteBuffer, NULL,
SEC_ERASE_SIZE);
/*
* Wait for the sector erse command to the
* FLASH to be completed
*/
while (1) {
/*
* Poll the status register of the device to determine
* when it completes, by sending a read status command
* and receiving the status byte
*/
XQspiPs_PolledTransfer(QspiPtr, ReadStatusCmd, FlashStatus,
sizeof(ReadStatusCmd));
/*
* If the status indicates the write is done, then stop
* waiting, if a value of 0xFF in the status byte is
* read from the device and this loop never exits, the
* device slave select is possibly incorrect such that
* the device status is not being read
*/
if ((FlashStatus[1] & 0x01) == 0) {
break;
}
}
Address += SECTOR_SIZE;
}
}
int FlashReadID(void) {
int Status;
/* Read ID in Auto mode.*/
WriteBuffer[COMMAND_OFFSET] = READ_ID;
WriteBuffer[ADDRESS_1_OFFSET] = 0x23; /* 3 dummy bytes */
WriteBuffer[ADDRESS_2_OFFSET] = 0x08;
WriteBuffer[ADDRESS_3_OFFSET] = 0x09;
Status = XQspiPs_PolledTransfer(&QspiInstance, WriteBuffer, ReadBuffer,
RD_ID_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
xil_printf("FlashID=0x%x 0x%x 0x%x\n\r", ReadBuffer[1], ReadBuffer[2],
ReadBuffer[3]);
return XST_SUCCESS;
}
void FlashQuadEnable(XQspiPs *QspiPtr) {
u8 WriteEnableCmd = { WRITE_ENABLE_CMD };
u8 ReadStatusCmd[] = { READ_STATUS_CMD, 0 };
u8 QuadEnableCmd[] = { WRITE_STATUS_CMD, 0 };
u8 FlashStatus[2];
if (ReadBuffer[1] == 0x9D) {
XQspiPs_PolledTransfer(QspiPtr, ReadStatusCmd, FlashStatus,
sizeof(ReadStatusCmd));
QuadEnableCmd[1] = FlashStatus[1] | 1 << 6;
XQspiPs_PolledTransfer(QspiPtr, &WriteEnableCmd, NULL,
sizeof(WriteEnableCmd));
XQspiPs_PolledTransfer(QspiPtr, QuadEnableCmd, NULL,
sizeof(QuadEnableCmd));
}
}
void QspiFlash_Init(void) {
int Status;
XQspiPs_Config *QspiConfig;
XQspiPs *QspiInstancePtr = &QspiInstance;
u16 QspiDeviceId = XPAR_PS7_UART_0_DEVICE_ID;
/* Initialize the QSPI driver so that it's ready to use*/
QspiConfig = XQspiPs_LookupConfig(QspiDeviceId);
Status = XQspiPs_CfgInitialize(QspiInstancePtr, QspiConfig,
QspiConfig->BaseAddress);
/* Perform a self-test to check hardware build*/
Status = XQspiPs_SelfTest(QspiInstancePtr);
/*
* Set Manual Start and Manual Chip select options and drive HOLD_B
* pin high.
*/
XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_MANUAL_START_OPTION |
XQSPIPS_FORCE_SSELECT_OPTION |
XQSPIPS_HOLD_B_DRIVE_OPTION);
/* Set the prescaler for QSPI clock*/
XQspiPs_SetClkPrescaler(QspiInstancePtr, XQSPIPS_CLK_PRESCALE_8);
/* Assert the FLASH chip select.*/
XQspiPs_SetSlaveSelect(QspiInstancePtr);
FlashReadID();
FlashQuadEnable(QspiInstancePtr);
}
/*****************************************************************************/
int QspiFlash_Write_Read_Demo(qspi_buff_t *pbuff) {
u32 err_cnt = 0;
XQspiPs *QspiInstancePtr = &QspiInstance;
if(pbuff->wr_en){
FlashErase(QspiInstancePtr, pbuff->flash_start_addr, pbuff->wr_length);
/*
* Write the data in the write buffer to the serial FLASH a page at a
* time, starting from TEST_ADDRESS
*/
for (int Page = 0; Page < pbuff->wr_length/PAGE_SIZE+1; Page++) {
FlashWrite(QspiInstancePtr, (Page * PAGE_SIZE) + pbuff->flash_start_addr,
&pbuff->wr_buff[Page * PAGE_SIZE],
PAGE_SIZE, WRITE_CMD);
}
}
if(pbuff->rd_en){
/*
* Read the contents of the FLASH from TEST_ADDRESS, using Normal Read
* command. Change the prescaler as the READ command operates at a
* lower frequency.
*/
FlashRead(QspiInstancePtr, pbuff->flash_start_addr, pbuff->rd_buff,
pbuff->rd_length, READ_CMD);
/*
* Setup a pointer to the start of the data that was read into the read
* buffer and verify the data read is the data that was written
*/
u8* BufferPtr = &pbuff->rd_buff[DATA_OFFSET];
for (int Count = 0; Count < pbuff->rd_length; Count++) {
printf("%d: %x---%x\n", Count, BufferPtr[Count], pbuff->wr_buff[Count]);
if (BufferPtr[Count] != pbuff->wr_buff[Count]) {
err_cnt++;
}
}
}
return err_cnt;
}
void QspiFlash_Read_Demo(qspi_buff_t *pbuff) {
XQspiPs *QspiInstancePtr = &QspiInstance;
if(pbuff->rd_en){
/*
* Read the contents of the FLASH from TEST_ADDRESS, using Normal Read
* command. Change the prescaler as the READ command operates at a
* lower frequency.
*/
FlashRead(QspiInstancePtr, pbuff->flash_start_addr, pbuff->rd_buff,
pbuff->rd_length, READ_CMD);
/*
* Setup a pointer to the start of the data that was read into the read
* buffer and verify the data read is the data that was written
*/
u8* BufferPtr = &pbuff->rd_buff[DATA_OFFSET];
for (int Count = 0; Count < pbuff->rd_length; Count++) {
printf("%d: %x\n", Count, BufferPtr[Count]);
}
}
}#include "ACZ702_Lib/COMMON.h"
#include "xil_cache.h"
rec_buff_t rec_buffer;
qspi_buff_t qspi_buffer;
int main_uart_rx_tx(void)
{
PS_UART_Init(&UartPs1,XPAR_PS7_UART_0_DEVICE_ID, XUARTPS_OPER_MODE_NORMAL, 115200);
PS_UART_RX(&rec_buffer);
PS_UART_TX(&rec_buffer);
}
int main_uart_write_to_qspi(void)
{
PS_UART_Init(&UartPs1,XPAR_PS7_UART_0_DEVICE_ID, XUARTPS_OPER_MODE_NORMAL, 115200);
PS_UART_RX(&rec_buffer);
//PS_UART_TX(&rec_buffer);
QspiFlash_Init();
memcpy(qspi_buffer.wr_buff, rec_buffer.rec_buff, rec_buffer.recv_length);
qspi_buffer.wr_length=rec_buffer.recv_length;
qspi_buffer.rd_length=rec_buffer.recv_length;
qspi_buffer.wr_en=0;
qspi_buffer.rd_en=1;
qspi_buffer.flash_start_addr=0x00400000;
u32 err_cnt = QspiFlash_Write_Read_Demo(&qspi_buffer);
xil_printf("Error_cnt=%d\r\n", err_cnt);
return 0;
}
int main_qspi_read_only(void)
{
QspiFlash_Init();
qspi_buffer.rd_length=142560;
qspi_buffer.rd_en=1;
qspi_buffer.flash_start_addr=0x00400000;
QspiFlash_Read_Demo(&qspi_buffer);
return 0;
}
int main(void)
{
//main_uart_rx_tx();
//main_uart_write_to_qspi();
main_qspi_read_only();
}