microblaze与zynq共存情形(之九) - minichao9901/TangNano-20k-Zynq-7020 GitHub Wiki
不使用local memory。
关闭了mb的Cache。mb的data使用DP->GP0接口访问。看能否搞定，解决程序在ddr中运行？
手动在ld文件前面新增加几个section，手动将前几十个字节的vectors放置到指定的位置（ddr中）
/* Specify the default entry point to the program */
ENTRY(_start)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.vectors.reset 0x10000000 : {
*(.vectors.reset)
}
.vectors.sw_exception 0x10000008 : {
*(.vectors.sw_exception)
}
.vectors.interrupt 0x10000010 : {
*(.vectors.interrupt)
}
.vectors.hw_exception 0x10000020 : {
*(.vectors.hw_exception)
} 
注意要在ddr_base地址上偏移0x50地址，前0x50以内放置mb的vectors。
#include <stdio.h>
#include "xparameters.h"
#include "xgpio.h"
#include "sleep.h"
#include "xil_cache.h"
#define GPIO_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID // 根据实际硬件配置修改
#define LED_CHANNEL 1
void test_ddr(UINTPTR addr, u32 length, u8 mode)
{
for(UINTPTR p=addr; p<addr+length; p+=4){
Xil_Out32(p,0x11223344);
}
for(UINTPTR p=addr; p<addr+length; p+=4){
int v= Xil_In32(p);
if(mode==0){
xil_printf("%p->%x\r\n",p,v);
}
else if(mode==1 && v!=11223344){
xil_printf("%p\r\n",p);
}
}
}
int main() {
XGpio gpio;
int Status;
usleep(50000);
Xil_DCacheDisable();
xil_printf("Microblaze GPIO test!\r\n");
// 初始化GPIO
Status = XGpio_Initialize(&gpio, GPIO_DEVICE_ID);
if (Status != XST_SUCCESS) {
printf("GPIO Initialization failed\n");
return XST_FAILURE;
}
// 设置GPIO为输出
XGpio_SetDataDirection(&gpio, LED_CHANNEL, 0x00);
while (1) {
// scanf("%c",&c);
// while(c!='c');
xil_printf("Microblaze Print Now!\r\n");
test_ddr(0x11000000,16,0); //test ddr
test_ddr(0xfffc0000,16,0); //test ocm, remap模式才可以访问
test_ddr(0xfffd0000,16,0); //test ocm, remap模式才可以访问
test_ddr(0xfffe0000,16,0); //test ocm, remap模式才可以访问
test_ddr(0xffff0000,16,0); //test ocm, remap模式才可以访问
test_ddr(0x00000000,16,0); //test ocm0, 默认非remap模式可以访问
test_ddr(0x00010000,16,0); //test ocm1, 默认非remap模式可以访问
test_ddr(0x00020000,16,0); //test ocm2, 默认非remap模式可以访问
test_ddr(0xFFFF0000,16,0); //test ocm3, 默认非remap模式可以访问
// 依次翻转四个GPIO引脚
XGpio_DiscreteWrite(&gpio, LED_CHANNEL, 0b0001);
usleep(500000/10); // 等待500毫秒
XGpio_DiscreteWrite(&gpio, LED_CHANNEL, 0b0010);
usleep(500000/10);
XGpio_DiscreteWrite(&gpio, LED_CHANNEL, 0b0100);
usleep(500000/10);
XGpio_DiscreteWrite(&gpio, LED_CHANNEL, 0b1000);
usleep(500000/10);
}
return 0;
}- 只负责remap，其实不是必须的。不用zynq，mb也是可以在运行的。关键在于正确设置mb的ld文件。
- 我自己写的remap函数
#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "xgpio.h"
void Xil_Remap_OCM(void)
{
xil_printf("%x\r\n",Xil_In32(0xf8000910)); //read slcr.ocm_cfg
Xil_Out32(0xf8000000+0x08,0xdf0d); //slcr.unlock
Xil_Out32(0xf8000910,0x000f); //slcr.ocm_cfg(remap ocm from 0x00000000->0xfffc0000)
Xil_Out32(0xf8000000+0x08,0x0); //slcr_unlock
xil_printf("%x\r\n",Xil_In32(0xf8000910)); //read slcr.ocm_cfg again
}
int main()
{
init_platform();
Xil_Remap_OCM();
cleanup_platform();
return 0;
}- xilinx官方提供的remap函数（功能更多）
#include "xil_io.h"
#include "xil_mmu.h"
#include "xpseudo_asm.h"
#include "remap_ocm.h"
#include <xil_cache.h>
#define GPIO_BASE 0xE000A000
#define GPIO_DIRM (GPIO_BASE+0x0284)
#define GPIO_MASK_DATA (GPIO_BASE+0x0010)
// OCM memory used to communicate with CPU0
#define COMM_VAL (*(volatile u32 *)(0xFFFF0000))
// Remap all 4 64KB OCM to top of memory starting at 0xFFFC0000
// Open address filtering to include DDR at 0x00000000
#define MY_REMAP() __asm__ __volatile__(\
"mov r5, #0x03 \n"\
"mov r6, #0 \n"\
"LDR r7, =0xF8000000 /* SLCR base address */ \n"\
"LDR r8, =0xF8F00000 /* MPCORE base address */ \n"\
"LDR r9, =0x0000767B /* SLCR lock key */ \n"\
"mov r10,#0x1F \n"\
"LDR r11,=0x0000DF0D /* SLCR unlock key \n"\
"dsb \n"\
"isb /* make sure it completes */ \n"\
"pli do_remap /* preload the instruction cache */ \n"\
"pli do_remap+32 \n"\
"pli do_remap+64 \n"\
"pli do_remap+96 \n"\
"pli do_remap+128 \n"\
"pli do_remap+160 \n"\
"pli do_remap+192 \n"\
"isb /* make sure it completes */ \n"\
"b do_remap \n"\
".align 5, 0xFF /* forces the next block to a cache line alignment */ \n"\
"do_remap: /* Unlock SLCR */ \n"\
"str r11, [r7, #0x8] /* Configuring OCM remap value */ \n"\
"str r10, [r7, #0x910] /* Lock SLCR */ \n"\
"str r9, [r7, #0x4] /* Disable SCU & address filtering */ \n"\
"str r6, [r8, #0x0] /* Set filter start addr to 0x00000000 */ \n"\
"str r6, [r8, #0x40] /* Enable SCU & address filtering */ \n"\
"str r5, [r8, #0x0] \n"\
"dmb \n"\
);
int main()
{
// Remap all 4 64KB blocks of OCM to top of memory
MY_REMAP();
// Disable L1 cache for OCM
Xil_SetTlbAttributes(0xFFFC0000,0x04de2); // S=b0 TEX=b100 AP=b11, Domain=b1111, C=b0, B=b0
COMM_VAL = 0;
/**********************************************************
* mb bootloop
* If not using FSBL to download Microblaze elf to DDR
* the reset vector of the Microblaze needs to contain
* a 'branch to self' in order to provide the Microblaze
* valid code to run before before the debugger can halt
* the Microblaze and download the application that
* places valid code at the Microblaze's reset vector
*
* If using SDK/XMD to download the Microblaze application
* uncomment the following two lines of code
**********************************************************/
Xil_Out32(0x30000000, 0xb8000000);
Xil_DCacheFlush();
///////////////////////////////////////////////
//Take PL out of reset
//Enable emio bit 0
//Xil_Out32(GPIO_DIRM, 0x1);
//Set emio[0] to release PL reset
//Xil_Out32(GPIO_MASK_DATA, 0xfffe0001);
///////////////////////////////////////////////
// Loop forever
// while(1) {
// xil_printf("CPU0: Hello World\n\r");
//
// // Wait until UART TX FIFO is empty
// while ((Xil_In32(STDOUT_BASEADDRESS + 0x2C) & 0x08) != 0x08);
//
// COMM_VAL = 1;
// while(COMM_VAL == 1);
// }
return 0;
}
以上分别是：
1）mb-only的运行结果，可见在mb中可以正确运行，但是只能读写ddr+ocm3的数据。 读写ocm_lower_addr错误，读写ocm_higher_addr也不行。
2）mb+zynq_remap(官方)的运行结果：可见mb+zyqn_remap，可以正确读写ddr/ocm_higher_addr/ocm3的数据。读写ocm_lower_addr错误。
3）mb+zyqn_remap(我写的)的运行结果：与前面用官方的remap结果一样。
存在的问题：运行速度比较慢，不是正确的情况，看样子直接在ddr中运行，没有cache是很慢的。
/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: Xilinx EDK 14.5 EDK_P.58f */
/* */
/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
/* */
/* Description : MicroBlaze Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;
/* Define Memories in the system */
MEMORY
{
ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR : ORIGIN = 0x10000050, LENGTH = 0x0FFFFFB0
ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
}
/* Specify the default entry point to the program */
ENTRY(_start)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.vectors.reset 0x10000000 : {
*(.vectors.reset)
}
.vectors.sw_exception 0x10000008 : {
*(.vectors.sw_exception)
}
.vectors.interrupt 0x10000010 : {
*(.vectors.interrupt)
}
.vectors.hw_exception 0x10000020 : {
*(.vectors.hw_exception)
}
.text : {
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.init : {
KEEP (*(.init))
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.fini : {
KEEP (*(.fini))
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
PROVIDE(__DTOR_END__ = .);
PROVIDE(___DTORS_END___ = .);
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.sdata2 : {
. = ALIGN(8);
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
. = ALIGN(8);
__sdata2_end = .;
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.data : {
. = ALIGN(4);
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
__data_end = .;
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.got : {
*(.got)
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.got1 : {
*(.got1)
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.got2 : {
*(.got2)
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.eh_frame : {
*(.eh_frame)
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.jcr : {
*(.jcr)
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.sdata : {
. = ALIGN(8);
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.sbss (NOLOAD) : {
. = ALIGN(4);
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
. = ALIGN(8);
__sbss_end = .;
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.bss (NOLOAD) : {
. = ALIGN(4);
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
__bss_end = .;
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(8);
_heap = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
.stack (NOLOAD) : {
_stack_end = .;
. += _STACK_SIZE;
. = ALIGN(8);
_stack = .;
__stack = _stack;
} > ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR_ps7_ddr_0_S_AXI_HP0_BASEADDR_ps7_ddr_0_S_AXI_HP1_BASEADDR
_end = .;
}/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: Xilinx EDK 14.5 EDK_P.58f */
/* */
/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
/* */
/* Description : Cortex-A9 Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x00100000, LENGTH = 0x0FF00000
ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
*(.vectors)
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > ps7_ddr_0_S_AXI_BASEADDR
.init : {
KEEP (*(.init))
} > ps7_ddr_0_S_AXI_BASEADDR
.fini : {
KEEP (*(.fini))
} > ps7_ddr_0_S_AXI_BASEADDR
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.sdata2 : {
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.data : {
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.got : {
*(.got)
} > ps7_ddr_0_S_AXI_BASEADDR
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.eh_frame : {
*(.eh_frame)
} > ps7_ddr_0_S_AXI_BASEADDR
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ddr_0_S_AXI_BASEADDR
.mmu_tbl (ALIGN(16384)) : {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.sbss (NOLOAD) : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.bss (NOLOAD) : {
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
} > ps7_ddr_0_S_AXI_BASEADDR
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(16);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > ps7_ddr_0_S_AXI_BASEADDR
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
. += _STACK_SIZE;
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
. = ALIGN(16);
__supervisor_stack = .;
_abort_stack_end = .;
. += _ABORT_STACK_SIZE;
. = ALIGN(16);
__abort_stack = .;
_fiq_stack_end = .;
. += _FIQ_STACK_SIZE;
. = ALIGN(16);
__fiq_stack = .;
_undef_stack_end = .;
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
} > ps7_ddr_0_S_AXI_BASEADDR
_end = .;
}