代码

• 一定要注意，if..elseif...else的顺序
• elseif(key==1)优先，elseif(dly_cnt==100)其次，最后才是计数逻辑

module tb7;
reg clk, rst_n;
initial clk=0;
always #10 clk=~clk;
initial begin
    rst_n=0;
    #1000;
    rst_n=1;
end 

reg key;
initial begin
    key=1;
    wait(rst_n==1);
    #100;
    key=0;
    #40;
    key=1;
    #30;
    key=0;
    #100;
    key=1;
    #200;
    key=0;
    #8000;
    key=1;
    #40;
    key=0;
    #80;
    key=1;

    #1000;

    key=0;
    #40;
    key=1;
    #30;
    key=0;
    #100;
    key=1;
    #200;
    key=0;
    #8000;
    key=1;
    #40;
    key=0;
    #80;
    key=1;
end

//1)
reg [15:0] dly_cnt;

always @(posedge clk or negedge rst_n)
if(rst_n==0)
    dly_cnt<=0;
else if(key==1)
    dly_cnt<=0;    
else if(dly_cnt==100)
    dly_cnt<=100;
else
    dly_cnt++;
    
assign key_pulse=(dly_cnt==100-1);


endmodule

按键检测用verilog写确实比较简单，比c语言简单多了。