小梅哥测试代码（供学习） - minichao9901/TangNano-20k-Zynq-7020 GitHub Wiki
D1
特点：wait()用法, @(clk)用法
`timescale 1ns/1ns
module adc128s102_tb;
reg Clk;
reg Reset_n;
reg Conv_Go;
reg [2:0]Addr;
wire Conv_Done;
wire[11:0]Data;
wire ADC_SCLK;
wire ADC_CS_N;
wire ADC_DIN;
reg ADC_DOUT;
adc128s102 adc128s102(
.Clk(Clk),
.Reset_n(Reset_n),
.Conv_Go(Conv_Go),
.Addr(Addr),
.Conv_Done(Conv_Done),
.Data(Data),
.ADC_SCLK(ADC_SCLK),
.ADC_CS_N(ADC_CS_N),
.ADC_DIN(ADC_DIN),
.ADC_DOUT(ADC_DOUT)
);
initial Clk = 1;
always #10 Clk = ~Clk;
initial begin
Reset_n = 0;
Conv_Go = 0;
Addr = 0;
#201;
Reset_n = 1;
#200;
Conv_Go = 1;
Addr = 3;
#20;
Conv_Go = 0;
wait(!ADC_CS_N);
//16'h0A58
@(negedge ADC_SCLK);
ADC_DOUT = 0; //DB15
@(negedge ADC_SCLK);
ADC_DOUT = 0; //DB14
@(negedge ADC_SCLK);
ADC_DOUT = 0; //DB13
@(negedge ADC_SCLK);
ADC_DOUT = 0; //DB12
@(negedge ADC_SCLK);
ADC_DOUT = 1; //DB11
@(negedge ADC_SCLK);
ADC_DOUT = 0; //DB10
@(negedge ADC_SCLK);
ADC_DOUT = 1; //DB9
@(negedge ADC_SCLK);
ADC_DOUT = 0; //DB8
@(negedge ADC_SCLK);
ADC_DOUT = 0; //DB7
@(negedge ADC_SCLK);
ADC_DOUT = 1; //DB6
@(negedge ADC_SCLK);
ADC_DOUT = 0; //DB5
@(negedge ADC_SCLK);
ADC_DOUT = 1; //DB4
@(negedge ADC_SCLK);
ADC_DOUT = 1; //DB3
@(negedge ADC_SCLK);
ADC_DOUT = 0; //DB2
@(negedge ADC_SCLK);
ADC_DOUT = 0; //DB1
@(negedge ADC_SCLK);
ADC_DOUT = 0; //DB0
wait(ADC_CS_N);
#20000;
Conv_Go = 1;
Addr = 7;
#20;
Conv_Go = 0;
wait(!ADC_CS_N);
//16'h0893
@(negedge ADC_SCLK);
ADC_DOUT = 0;
@(negedge ADC_SCLK);
ADC_DOUT = 0;
@(negedge ADC_SCLK);
ADC_DOUT = 0;
@(negedge ADC_SCLK);
ADC_DOUT = 0;
@(negedge ADC_SCLK);
ADC_DOUT = 1;
@(negedge ADC_SCLK);
ADC_DOUT = 0;
@(negedge ADC_SCLK);
ADC_DOUT = 0;
@(negedge ADC_SCLK);
ADC_DOUT = 0;
@(negedge ADC_SCLK);
ADC_DOUT = 1;
@(negedge ADC_SCLK);
ADC_DOUT = 0;
@(negedge ADC_SCLK);
ADC_DOUT = 0;
@(negedge ADC_SCLK);
ADC_DOUT = 1;
@(negedge ADC_SCLK);
ADC_DOUT = 0;
@(negedge ADC_SCLK);
ADC_DOUT = 0;
@(negedge ADC_SCLK);
ADC_DOUT = 1;
@(negedge ADC_SCLK);
ADC_DOUT = 1;
wait(ADC_CS_N);
#200;
#2000;
$stop;
end
endmodule
D2
特点：while() begin @(clk)... end的用法
`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/01/02 13:53:39
// Design Name:
// Module Name: bram_sync_fifo_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bram_sync_fifo_test();
reg Reset;
reg Clk;
reg [7:0]din;
reg wr_en;
reg rd_en;
wire [7:0]dout;
wire full;
wire almost_full;
wire wr_ack;
wire overflow;
wire empty;
wire almost_empty;
wire valid;
wire underflow;
wire [7:0]data_count;
bram_sync_fifo bram_sync_fifo (
.clk(Clk), // input wire clk
.srst(Reset), // input wire srst
.din(din), // input wire [7 : 0] din
.wr_en(wr_en), // input wire wr_en
.rd_en(rd_en), // input wire rd_en
.dout(dout), // output wire [7 : 0] dout
.full(full), // output wire full
.almost_full(almost_full), // output wire almost_full
.wr_ack(wr_ack), // output wire wr_ack
.overflow(overflow), // output wire overflow
.empty(empty), // output wire empty
.almost_empty(almost_empty), // output wire almost_empty
.valid(valid), // output wire valid
.underflow(underflow), // output wire underflow
.data_count(data_count) // output wire [7 : 0] data_count
);
initial Clk = 1;
always #10 Clk = ~Clk;
initial begin
Reset = 1'b1;
wr_en = 1'b0;
rd_en = 1'b0;
din = 8'hff;
#21;
Reset = 1'b0;
//写操作，从0到255，共256个数据
while(full == 1'b0)
begin
@(posedge Clk);
#1;
wr_en = 1'b1;
din = din + 1'b1;
end
//再多写一个数据，看overflow的变化
din = 8'hf0;
@(posedge Clk);
#1;
wr_en = 1'b0;
#2000;
//读操作，读256次
while(empty == 1'b0)
begin
@(posedge Clk);
#1;
rd_en = 1'b1;
end
//再多给一个读使能，看underflow的变化
@(posedge Clk);
#1;
rd_en = 1'b0;
//复位
#200;
Reset = 1'b1;
#21;
Reset = 1'b0;
#2000;
$stop;
end
endmodule
D3
特点：defparam的用法
`timescale 1ns / 1ns
module led_ctrl_tb();
reg Clk;
reg Reset_n;
wire Led;
reg [7:0]SW;
led_ctrl3 led_ctrl3(
.Clk(Clk),
.Reset_n(Reset_n),
.SW(SW),
.Led(Led)
);
//defparam led_ctrl1.TIME_UNIT_MS = 1;
defparam led_ctrl3.MCNT0 = 12500-1;
defparam led_ctrl3.MCNT2 = 50_000-1;
initial Clk = 1;
always #10 Clk = ~Clk;
initial begin
Reset_n = 0;
SW=8'b1010_1001;
#201;
Reset_n = 1;
#40000000;
$stop;
end
endmodule
D4
特点：repeat begin ....end的用法
`timescale 1ns / 1ps
module ram_tb;
reg clka ;
reg ena ;
reg wea ;
reg [15:0] addra;
reg [15:0] dina ;
reg clkb ;
reg enb ;
reg [15:0] addrb;
wire [15:0] doutb;
ram ram (
.clka (clka), // input wire clka
.ena (ena), // input wire ena
.wea (wea), // input wire [0 : 0] wea
.addra(addra), // input wire [15 : 0] addra
.dina (dina), // input wire [15 : 0] dina
.clkb (clkb), // input wire clkb
.enb (enb), // input wire enb
.addrb(addrb), // input wire [15 : 0] addrb
.doutb(doutb) // output wire [15 : 0] doutb
);
initial clka = 1; always #10 clka = ~clka;
initial clkb = 1; always #15 clkb = ~clkb;
initial begin
ena = 0;
wea = 0;
addra = 0;
dina = 0;
addrb = 0;
enb = 0;
// 写入 写满
#201;
repeat(65536) begin
ena = 1;
wea = 1;
#20;
addra = addra + 1;
dina = dina + 1;
end
ena = 0;
wea = 0;
#20000;
// 读出
addrb = 65535;
#300;
repeat(65536) begin
enb = 1;
#30;
addrb = addrb - 1;
end
#2000;
$stop;
end
endmodule
D5
特点：repeat() begin....end的用法
`timescale 1ns / 1ps
module rom_tb();
reg clka;
reg [9:0] addra;
wire [9:0] douta;
rom ROM (
.clka(clka), // input wire clka
.addra(addra), // input wire [9 : 0] addra
.douta(douta) // output wire [9 : 0] douta
);
initial clka = 1;
always #10 clka = !clka;
initial begin
addra = 100;
#201;
repeat(3000) begin
addra = addra + 1'd1;
#20;
end
#2000;
$stop;
end
endmodule
D6
特点：与外设模块的交互，用set start/data....wait(end==1)的方法交互
`timescale 1ns / 1ps
module TLV5618_Driver_tb();
reg Clk;
reg Rst_n;
reg [15:0]DAC_DATA;
reg Set_Go;
wire Set_Done;
wire DAC_CS_N;
wire DAC_DIN;
wire DAC_SCLK;
TLV5618_Driver TLV5618_Driver(
.Clk(Clk),
.Rst_n(Rst_n),
.DAC_DATA(DAC_DATA),
.Set_Go(Set_Go),
.Set_Done(Set_Done),
.DAC_CS_N(DAC_CS_N),
.DAC_DIN(DAC_DIN),
.DAC_SCLK(DAC_SCLK)
);
initial Clk = 1;
always#10 Clk = ~Clk;
initial begin
Rst_n = 0;
Set_Go = 0;
DAC_DATA = 0;
#201;
Rst_n = 1;
#200;
DAC_DATA = 16'hC_AAA;
Set_Go = 1;
#20;
Set_Go = 0;
#200;
wait(Set_Done);
#20001;
DAC_DATA = 16'h4_555;
Set_Go = 1;
#20;
Set_Go = 0;
#200;
wait(Set_Done);
#20001;
DAC_DATA = 16'h1_555;
Set_Go = 1;
#20;
Set_Go = 0;
#200;
wait(Set_Done);
#20001;
DAC_DATA = 16'hf_555;
Set_Go = 1;
#20;
Set_Go = 0;
#200;
wait(Set_Done);
#20000;
$stop;
end
endmodule
D7
`timescale 1ns / 1ps
module uart_byte_rx_tb();
reg Clk;
reg Reset_n;
reg uart_rx;
wire Rx_Done;
wire [7:0]Rx_Data;
uart_byte_rx uart_byte_rx(
.Clk(Clk),
.Reset_n(Reset_n),
.uart_rx(uart_rx),
.Rx_Done(Rx_Done),
.Rx_Data(Rx_Data)
);
initial Clk = 1;
always #10 Clk= ~Clk;
initial begin
Reset_n = 0;
uart_rx = 1;
#201;
Reset_n = 1;
#200;
//8'b0101_0101
uart_rx = 0; #(5208*20); //起始位
uart_rx = 1; #(5208*20); //bit0
uart_rx = 0; #(5208*20); //bit1
uart_rx = 1; #(5208*20); //bit2
uart_rx = 0; #(5208*20); //bit3
uart_rx = 1; #(5208*20); //bit4
uart_rx = 0; #(5208*20); //bit5
uart_rx = 1; #(5208*20); //bit6
uart_rx = 0; #(5208*20); //bit7
uart_rx = 1; #(5208*20); //停止位
#(5208*20*10);
//8'b1010_1010
uart_rx = 0; #(5208*20); //起始位
uart_rx = 0; #(5208*20); //bit0
uart_rx = 1; #(5208*20); //bit1
uart_rx = 0; #(5208*20); //bit2
uart_rx = 1; #(5208*20); //bit3
uart_rx = 0; #(5208*20); //bit4
uart_rx = 1; #(5208*20); //bit5
uart_rx = 0; #(5208*20); //bit6
uart_rx = 1; #(5208*20); //bit7
uart_rx = 1; #(5208*20); //停止位
#(5208*20*10);
//8'b1111_0000
uart_rx = 0; #(5208*20); //起始位
uart_rx = 0; #(5208*20); //bit0
uart_rx = 0; #(5208*20); //bit1
uart_rx = 0; #(5208*20); //bit2
uart_rx = 0; #(5208*20); //bit3
uart_rx = 1; #(5208*20); //bit4
uart_rx = 1; #(5208*20); //bit5
uart_rx = 1; #(5208*20); //bit6
uart_rx = 1; #(5208*20); //bit7
uart_rx = 1; #(5208*20); //停止位
#(5208*20*10);
//8'b0000_1111
uart_rx = 0; #(5208*20); //起始位
uart_rx = 1; #(5208*20); //bit0
uart_rx = 1; #(5208*20); //bit1
uart_rx = 1; #(5208*20); //bit2
uart_rx = 1; #(5208*20); //bit3
uart_rx = 0; #(5208*20); //bit4
uart_rx = 0; #(5208*20); //bit5
uart_rx = 0; #(5208*20); //bit6
uart_rx = 0; #(5208*20); //bit7
uart_rx = 1; #(5208*20); //停止位
#(5208*20*10);
$stop;
end
endmodule