Tools and Toolchain - micro-FPGA/riscv-contest-2018 GitHub Wiki
FPGA Tools
Libero, iCEcube2 and Radiant require a license, free license is available.
It is usually much easier to install the node locked license.
Libero
This is the only FPGA tool for Microsemi targets, free silver license can be used
Note - installation on Window PC works out of the box.
iCEcube2
NotE: iCEcube2 does not include Programmer so Diamond should be installed as well even if only used for Programming the FPGA.
Radiant
iceStorm
Open source FPGA toolchain supports iCE40, no license needed. Setup maybe complicated as it most likely requires the toolchain to be fully recompiled from sources.
Would be nice to use iceStorm using WLS Window Linux Subsytem
Debug Tools (FPGA)
Reveal Debugger included with Radiant doesn't seem to work at all.
If you have issues with Identify claiming to require a separate (paid) license please uninstall and re-install Libero. Identify should then start without the "license required" dialog popup.
Libero SmartDebug provides some visibility to read out flip-flop and RAM content from FPGA.
Simulation Tools
OVPsim
This is free commercial tool, you can get free personal use license (flexlm) keys for 90 days.
RISCV demos are included, running Dhrystone demos out of the box will give
Measured time too small to obtain meaningful results
message - so it seems the out of the box demos are not tested.
renode
Amazing free and open source tool. Easy download, runs out of the box. Support for Microsemi MI-V included.
Verilator
This is a trick, you can take some known RISC-V verilog code, run it through verilator and use the resulting executable as mini Simulator.
Compiler Tools
Notes:
GCC generates verilog memory files with as bytes, they would most likely load wrong with verilog $readmem, conversion to 32 bit mem file format is possible using python script from picorv32 project hex8tohex32.py
Verilator on Windows
The old binaries can be used, either MSVC Express or Mingw can be used to compile the verilated code
Compiling with MSVC
Compiling with MINGW
set VERI=C:\riscv\verilator-3.841
set INC=%VERI%\include
gcc -I .\obj_dir -I %INC% %INC%\verilated.cpp .\obj_dir\Vtestbench.cpp .\obj_dir\Vtestbench__Syms.cpp testbench.cc -lstdc++
The important switch is the -lstdc++