OPT1 - mattrighetti/leiserson-retiming GitHub Wiki

Implementation

Given a synchronous circuit graph_prop, this algorithm determines a retiming r such that clock_symbol is as small as possible.

  1. Compute W and D using Algorithm WD.
  2. Sort the element sin the range of D.
  3. Binary search among the elements D(u, v) for the minimum achievable clock period. To test whether each potential clock period c is feasible, apply the Bellman-Ford algorithm to determine whether the conditions in theorem 7 can be satisfied.

See in code

Time Complexity

opt1_time_complex

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