FEAS - mattrighetti/leiserson-retiming GitHub Wiki

Implementation

Given a synchronous circuit graph_prop and a desired clock period c, this algorithm produces a retiming r of G such that G_r is a synchronous circuit with clock period clock_minor_c, if such a retiming exists.

  1. For each vertex vinV, set deltaVZ.
  2. Repeat the following V-1 times:
    1. Compute graph G_r with the existing values for r.
    2. Run Algorithm CP on the graph G_r to determine deltaV for each vertex vinV.
    3. For eachv suchthat deltaVC, set deltaVR
  3. Run Algorithm CP on the circuit G_r. If clock_up_c, then no feasible retiming exists. Otherwise, r is the desired retiming.

See in code

Time Complexity

feas_time_complex

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