LabNotes - mattlacey/Lacey-Mk-I GitHub Wiki

http://www.microchip.com/wwwproducts/en/ATF1504AS

Naming.

Active-low signals use # notation, i.e. HALT# is active-low.

MC68000P12

Datasheet

Clock Module

CLK

The clock input should not be gated off at any time, and the clock signal must conform to minimum and maximum pulse-width times.

Clock can run 4-12.5MHz

Minumum: 4MHz, cycle time 250ns, pulse width (1.5V to 1.5V) 125ns Maximum: 12MHz, cycle time 80ns, pulse width 35 ns Max rise & fall time: 5ns frmo 0.8V to 2.0V

Power Module

555 Monostable Calculator

Reset (RESET#)

The external assertion of this bidirectional signal along with the assertion of HALT# starts a system initialization sequence by resetting the processor. The processor assertion of RESET# (from executing a RESET instruction) resets all external devices of a system without affecting the internal state of the processor. To reset both the processor and the external devices, the RESET# and HALT# input signals must be asserted at the same time.

Halt (HALT#)

An input to this bidirectional signal causes the processor to stop bus activity at the completion of the current bus cycle. This operation places all control signals in the inactive state and places all three-state lines in the high-impedance state. When the processor has stopped executing instructions (in the case of a double bus fault condition, for example), the HALT line is driven by the processor to indicate the condition to external devices

Startup

HALT# and RESET# must be asserted for a minimum of 100ms.

Reset

HALT# and RESET# must be asserted for 10 clock cycles

Signal Table

Signals

Pinout

Pinout

Read/Write Bus Cycles

Read

CPU

  1. R/W set to read
  2. Function code on FC0-FC2
  3. Address lines set
  4. Assert AS (LOW)
  5. Assert UDS and LDS (LOW)

SYS

  1. Decode
  2. Place data
  3. Assert DTACK (LOW)

CPU

  1. Latch Data
  2. Negate UDS and LDS
  3. Negate AS

SYS

  1. Remove data
  2. Negate DTACK

Write

  1. Place fn code on FC0-FC2
  2. Address lines set
  3. Assert AS (LOW)
  4. Set R/W to Write (LOW)
  5. Place data on bus
  6. Assert UDS and LDS (LOW)

SYS

  1. Decode address
  2. Store data
  3. Assert DTACK (LOW)

CPU

  1. Negate UDS & LDS
  2. Negate AS
  3. Remove data
  4. Set R/W to Read (HIGH)

SYS

  1. Negate DTACK

Simple Implementation

If data strobes are pulled low then we're good to go.

NAND(UDS, LDS) then DTACK -> LOW

For write operations UDS and LDS are strobed a clock cycle after AS, so if R/W is low and AS is LOW then we're also good.

(!RW && !AS) || !UDS || !LDS

DTACK needs to be asserted low after a delay, ergo shift register. DTACK needs to be negated as soon as the controlling line is negated (per above), this can be achieved with the CLR on the 74595, but it's inverted.

!UDS || !LDS == NAND(UDS, LDS) -> (x)

x -> CLR on 74595, SDATA = VCC -> (y)

NOT((y)) -> DTACK**

#SRAM

Datasheet: http://www.alliancememory.com/pdf/AS6C4008.pdf

2x 512K X 8 BIT

SYMBOL | DESCRIPTION A0-A18 | AddressInputs DQ0–DQ7 | DataInputs/Outputs CE# | Chip EnableInputs WE# | WriteEnableInput OE# | OutputEnableInput VCC | PowerSupply VSS | Ground NC | NoConnection

Pinout:

Ram Pinout

Memory Map

CPU: 24 bit bus, 23 bit external EEPROM: 15 bit bus (2 x 32KB) SRAM: 19 bit bus (2 x 512KB, 2 Pages)

Using 512 KB pages. A19-A23 indicate page.

First 1KB of address space is used for exception vectors.

--------
0x000000 Bottom of ROM 
    |
0x00FFFF Top of ROM (2 x 32KB)
--------
0x010000 I/O
    |
0x07FFFF
--------
0x080000 Bottom of RAM
    |
0x100000 Top of RAM (1MB with two chips)
    |
0xFFFFFF Top of RAM capacity (future)

Decoding with 1MB RAM:

(A20 || A21) -> RAMSEL

Decoding ROM

ROM should be selected (ROMSEL = 0) when RAMSEL is 0 and UDS/LDS is 0, so (RAMSEL || UDS/LDS). TODO: Factor in AS?

Decoding RAM

Use AS to qualify address as valid, use to drive CS on the RAM chips.

RAMSEL !RAMSEL     AS   OR(CS) 
  0        1        0    1   
  1        0        0    0    
  0        1        1    1   
  1        0        1    1

New Decoding

Need another page for IO, potentially need more in the future. Decode 3 address lines (A20 - A22) to give 8 pages.

Page Area 0 ROM 1 RAM 2 RAM 3 Serial IO 4-8 Reserved

A20 A21 0 0 - ROM - NOR(A20, A21) 1 0 - RAM - NOT(XOR(A20, A21)) 0 1 - RAM - NOT(XOR(A20, A21)) 1 1 - I/O - NAND(A20, A21)

Could just AND > NOT A20 & A21 (NOR).

RAM R/W

RAM should be selected when RAMSEL is 0 and UDS/LDS is 0, so CS driven as above. OE needs to be driven low for reads and high for writes. WE needs to be low for writes, but high while addresses are being changed.

OE and WE are both driven by UDS/LDS, and which one of the two is controlled by RW from the 68k. RW is high for Read, and low for Write.


     RL RU WL WU
UDS  x  0  x  0
LDS  0  x  0  x
RW   1  1  0  0
RW'  0  0  1  1

RU Should be 0 when UDS = 0 and RW = 1
= UDS OR (RW')

L/UDS   RW   |  RW'  OR
 0      0    |   1    1
 0      1    |   0    0
 1      0    |   1    1
 1      1    |   0    1

WU Should be 0 when UDS = 0 and RW = 0

OR(UDS, RW)


RL OR(LDS, RW'))
RU OR(UDS, RW'))

WL OR(LDS, RW)
WU OR(UDS, RW)

Address Lines 17 and 18 are not wired for SRAM

EEPROM

Datasheet

AT28C256

Pin Out

Eeprom Pinout

Byte Read

The AT28C256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system.

7400 Chips

NAND - 7400

Find Me

NOR - 7402

7402 Nor

NOT - 7404

Sn 74 Hc 04 N

OR - 7432

Sn 74 Hct 32 N

AND - 7408

X Y  NAND   NOR
0 0   1      1
0 1   1      0
1 0   1      0
1 1   0      0

CPLD

JTAG Pinout

I/O/TDI (JTAG) 1  /  7
I/O/TMS (JTAG) 7  /  13
I/O/TCK (JTAG) 26 /  32
I/O/TDO (JTAG) 32 /  38

EEPROM Programmer

Chips on board: U1 - Low Addr U2 - High Addr U3 - Byte

Output from Arduino: U1 - Byte U2 - Low U3 - High

Scope Loop

00000008  4240                      12              clr.w   d0
0000000A  103C 00FF                 13              move.b  #$ff,d0
0000000E  207C 00080000             14              move.l  #$80000,a0
00000014  20C0                      15  inc:        move.l  d0,(a0)+
00000016  51C8 FFFC                 16              dbra    d0,inc
0000001A                            17              
0000001A  60EC                      18              bra.s   $0008

Reading from RAM?

A20 goes low before A19, even though 19 should be correct.

Rom After Flashing (Upper, Lower)

Address bus:

Working! Loop around!

MC68681P - DUART

https://learn.sparkfun.com/tutorials/terminal-basics/all http://www.auselectronicsdirect.com.au/arduino-usb-to-6-pin-ttl-serial-converter-module?gclid=EAIaIQobChMI9JDo1O7l1QIVyFe9Ch0yBQcBEAYYASABEgIItvD_BwE http://www.ti.com/product/TUSB3410

// DUART is mapped at F00000 
void printd(str)
char *str;
{
 /* simple debugging output */
 for(; *str != 0; str++)
 {
   while(!(*((char *)(0xF00000L+1)) & 0x4)); /* block until we can tx */
   *((char *)(0xF00000L+3)) = *str;
 }
}

CMOS Cystal Oscillator

Capacitors

101: 100 pF 103: 10 nF 470: 47 pF

Tantalum: 22 / 16+ 22uF