Ideas - matt-chv/electronics-design-patterns GitHub Wiki
Ideas
some ideas about the functions:
- either for signal processing or for control
- either in continuous time (analog) or discrete (digital) and from one another and vice-versa
- linear or non-linear
Signal processing
Notes
converters vs filters:
- converters seek to maximize energy transfer between input signal and output signal
- filters seek to remove energy from signal. The energy to be removed is decided at by the designer as
unwantedunder reasons specific to each design (anti-aliasing, noise reduction, x-talk removal, blockers, ...)
Convertors
* A2D:
* voltage to digital (most often simply refered to as `ADC`)
* current to digital
* time to digital (TDC)
* D2A
* DAC
* A2A
* voltage to voltage: buck, boost, sepic, AC/DC, ...
* current to voltage: TransImpedance, ...
overview in below table
| input\output | voltage | current | delta time | frequency | digital | R | C | L |
|---|---|---|---|---|---|---|---|---|
| voltage | DCDC, DCAC, ACDC | transconductance, V2I | VTC | V2F | ADC | |||
| current | TIA | current mirror | ? | ? | i-ADC | |||
| delta time | integrator | ? | pulse shrink/spread, delay | ? | TDC, timer | |||
| frequency | F2V | ? | ? | PLL, DLL, ... | FDC | |||
| digital | DAC | i-DAC | PWM? | PWM | DSP | dpot | ||
| R | ||||||||
| C | gyrator | |||||||
| L |
filters
* linear: LP / HP / BP ...
* non linear:
* deadband
* hysteresis
* rate limiter
* saturation
* ...
maths
* abs value
* sign
* sqrt
* summation
* exponential
* gain block
* log10
* min / max
* product
* greater than / lesser than
* derivative
* integral
Control Processing
logic
* and / or / xor / ...
* [fuzzy logic Zadeh operator](https://en.m.wikipedia.org/wiki/Fuzzy_logic#Fuzzy_logic_operators) `AND(X,Y)` == MIN, `OR`== MAX; `NOT(X)` == 1-X
* if then else
events
* edge triggered
* flip flop: SR/JK
* zero cross detect / - to + / + to - or ZCD
* time delay
signal routing
* look-up tables (many to many)
* DEMUX (1 to many)
* MUX (many to 1)
* switch (1 to 1)
Conversion to electricity
| Energy | Effect | Device |
|---|---|---|
| Thermic | Seebeck effect | type-K |
| Thermic | Seebeck effect | TEG |
| Thermic | Peltier effect | |
| Thermic | Thomson effect | |
| Light | Photovoltaic | c-Si |
| Light | Photovoltaic | a-Si |
| Light | Photovoltaic | OPV |
| Light | Photovoltaic | DSSC |
| Light | Photoelectric | LED |
| Light | Photoelectric | laser |
| Light | Photoelectric | photodiode |
| Light | Photoelectric | gas discharge |
| Chemical | Battery | Li-ion |
| Chemical | Battery | NiMH |
| Chemical | Battery | NiCd |
| Chemical | Battery | NiCd |
| Chemical | Battery | Fuel cell |
| Chemical | Photo-electrode | pH |
| Chemical | Photo-electrode | oRP |
| Chemical | electro-chemical | 3 lead cell |
| Chemical | electro-chemical | 2 lead cell |
| Thermal | Pyro-electric | |
| Tribo-electric | ||
| Cinetic | piezo-electric | microphone |
| Cinetic | piezo-electric | buzzer |
| Cinetic | ? | dynamo |
| Magnetic | ? | hall |
| Electro-Magnetic | ? | antenna |
Resistance dependant
- Light
- Strain
Capacitance dependant
*MOXFET
Schematics guidelines
Readability
- Power supplies use supply symbols (not wires) with useful names
- Positive supplies point up, ground and negative supplies point down. Always.
- All important nets are descriptively named
- Net “stubs” (nets visually connected to only one pin) use an “off-sheet” type of label with the correct In/Out/Bidirectional flag shape and cross reference info (sheet / location)
- Functional blocks are clearly labeled (plenty of whitespace around it, or maybe even a box)
- Functional blocks have text that describes what they do and their requirements (e.g., Vbatt to 3.3 V @ 1 A switching power supply”)
- There's a frame around the schematic
- It's clear where your power is coming from and what the power requirements are (V/I)
- Data flow (inputs, outputs, requirements) are clear and labeled
- All connectors have text that describes what they go to
- Route wires at a consistent distance from each other and avoid crossing net wires as possible
- Groups of nets above about ≥ 4 nets collected into buses
Schematic Symbols
- All symbols are schematic symbols, not packages (inputs on left, outputs on right, power on top and bottom)
- Pins have correct electrical rule check (ERC) direction (inputs, outputs, passives, etc)
- Components with symbolic shapes use those shapes (e.g, opamps are triangles)
Part values
- Capacitors have the appropriate voltage (usually ≥ 2x working voltage, also see this) and specify dielectric type if necessary
- Special case capacitors marked with power and tolerance
- Power dissipation checked on all resistors
- Special case resistors marked with power and tolerance
- Layout features that are circuit elements (e.g., copper inductor) are labeled in the schematic
IC Key Points
- MOSFETs oriented correctly WRT the body diode (!), with note if intentionally forward conducting
- Check IC part numbers reflect the correct package type
- Small, low ESR (e.g., ceramic) bypass capacitors on all IC supplies (check datasheet for values)
- Check voltage inputs and outputs match across power domains (e.g., 5V to 3.3V)
- Check that powered-off domains are not phantom powered by their inputs from other circuits (including test circuits, like UARTs)
- Check for UART TX/RX swaps (TX to RX, RX to TX)
- Check for pull-up/down resistors on open collector/drain outputs (e.g., I2C lines)
- Check for required pull-up/down resistors to set nets in a default state at power up
- Check for no floating nodes (especially during sleep states)
Design for Test
- Place test points on critical signals, especially power and ground
- Make sure crocodile or scope can easily use those when probing nearby nodes
- Consider the right side for SMT test points, or use through-hole test points (esp for bed-of-nails testers)
- Add debugging hardware (e.g., LEDs, UART connectors, jumpers, scope probe points, etc)
Design for Fail
- Group components in separable modularly powered blocks and use zero ohm resistors or cuttable jumpers to disconnect (especially for switching power supplies!)
- Unused pins (especially GPIO) should go to usable test points. Consider adding some random pull-up and pull-down resistors connected to a test point on the board, too
- Consider somehow encoding your PCB hardware revision in hardware (GPIO pullups, etc)
- UART (serial port) TX/RX are always mixed up, consider cuttable jumpers here
- Consider over-voltage/ polarity input protection if you or your user can screw this up
Electrical Rule checks (ERC)
- No unapproved errors OR warnings in the ERC
- All important excluded errors/warnings have a comment on why they’re approved
BOM Fixes
- Add “MFR” (Manufacturer) and “MPN” (Manufacturer’s Part Number) to all components as attributes
- Add a datasheet link and description to part attributes
MISC
- Peer reviewed by at least one person not involved in the design.
- Check stock at 1+ distributor
- Re-run ERC and double check your approved errors, looking for accidentally approved errors
- Revision Control:
- record changes to the schematic in a table or in nearby documentation
- Update your schematic version and/or date