| ARID[x:0] |
Master |
AXI3 and AXI4 |
Provides ID for each transaction |
| ARADDR[31:0] |
Master |
AXI3 and AXI4 |
Address for write request |
| ARLEN[7:0] |
Master |
AXI4 |
No.of transfers support in each transaction |
| ARSIZE[2:0] |
Master |
AXI3 and AXI4 |
No. of bytes to be transfer in each beat |
| ARBURST[1:0] |
Master |
AXI3 and AXI4 |
Indicates type of burst to be performed |
| ARLOCK |
Master |
AXI4 |
Indicates the atomic characteristics of the transaction |
| ARCACHE[3:0] |
Master |
AXI3 and AXI4 |
This signal indicates the system performance |
| ARPROT[2:0] |
Master |
AXI3 and AXI4 |
Provides system-level security and privileged access to each transaction |
| ARQoS[3:0] |
Master |
AXI4 |
Use to prioritize the transactions |
| ARREGION[3:0] |
Master |
AXI4 |
Region identifier |
| ARVALID |
Master |
AXI3 and AXI4 |
Use to validate the associated signal in order to pass valid information. |
| ARREADY |
slave |
AXI3 and AXI4 |
Indicates weather the slave is ready for the transactions |