RPi3, RPi4 Hardware - lulu98/projects-with-sel4 GitHub Wiki
Resources
High-Level Comparison
- High-level overview: https://medium.com/pi-top/raspberrypi4-f38f12633345
- BCM2711: https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md
- BCM2711 TRM: https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
- BCM2835 TRM: https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2835/BCM2835-ARM-Peripherals.pdf
- What changed: https://www.raspberrypi.org/forums/viewtopic.php?t=244479&start=25
Hardware Comparison
- BCM2711 TRM: https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
- BCM2835 TRM: https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2835/BCM2835-ARM-Peripherals.pdf
- ARMv7-A document: https://developer.arm.com/documentation/ddi0406/latest/
- ARMv8-A document: https://developer.arm.com/documentation/ddi0487/latest/
- GIC-400 document: https://developer.arm.com/documentation/ddi0471/b/
- Cortex-A53 document: https://developer.arm.com/documentation/ddi0500/j/
- Cortex-A72 document: https://developer.arm.com/documentation/100095/0003
- DTS files in the Linux Kernel
- Device Tree Documentation files in Linux Kernel
General Information
| Feature | RPi3 | RPi4 |
|---|---|---|
| ISA | ARMv8 | ARMv8 |
| Clock Speed | 1.4 GHz | 1.5 GHz |
| Processor | Cortex-A53 | Cortex-A72 |
| Process Technology | 40nm | 28nm |
| L1 Cache | 16kB D-Cache, 16kB I-Cache | 32kB D-Cache, 48kB I-Cache |
| L2 Cache | 512kB | 1MB |
| RAM | 1GB LPDDR2 | 2,4,8 GB LPDDR4 |
| Video Port | HDMI | 2 x uHDMI, 4K display, 60fps |
| GPU | VideoCore IV | VideoCore VI |
| USB | 4 x USB2.0 | 2 x USB2.0, 2 x USB3.0 |
| Ethernet | 300MBit/s (limited by USB2.0) | Gigabit ethernet (native) |
| Power Connection | uUSB | USB-C |
| Recommended power supply | 2.5 A | 3 A |
| GPIO | 40-pin header | 40-pin header (backwards compatible) |
| UART | 2 UARTs | 6 UARTs |
| Bluetooth | BT4.2 | BT5 |
| EEPROM | - | new EEPROM (no need for bootcode.bin) |
Ethernet
Resources
- Explanation: https://raspberrypi.stackexchange.com/questions/45130/why-do-the-usb-ports-and-ethernet-port-share-the-same-controller
- Additional information: https://www.raspberrypi.org/forums/viewtopic.php?t=227459
- RPi3 gigabit ethernet throughput: https://www.zdnet.com/article/raspberry-pi-3-model-b-arrives-faster-cpu-wi-fi-300mbps-ethernet/
RPi3
As the SoC on the RPi3 does not have an ethernet controller, only the USB controller could have been used for ethernet.
RPi3 ethernet is connected to USB 2.0 and shares bandwidth with the other USB ports. Activity on the USB ports can affect
ethernet performance. The Raspberry Pi 3 Model B+'s Gigabit Ethernet over USB 2.0 offers a maximum throughput of 300Mbps.
One option for improvement is to use a RPi3 over WiFi to bypass the USB interface. The WiFi chip doesn't share a bus with the USB sockets
and should run at full speed.
RPi4
With the RPi4 the USB hub with ethernet chip is gone, replaced by an Ethernet PHY chip driven by a MAC on the new SoC and a USB3 controller driven by the PCIe on the new SoC.
Mailbox
Resources
- BCM2837 TRM
- Mailbox Property Interface 1: https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
- Mailbox Property Interface 2: https://github.com/raspberrypi/documentation/blob/JamesH65-mailbox_docs/configuration/mailboxes/propertiesARM-VC.md
RPi3
The RPi3 consists of the VideoCore GPU and the Cortex-A53 ARM cores. The properties interface allows setting, getting and testing of
various properties. It is the main method for accessing user data on the Videocore from ARM space.
The interrupts from doorbell 0,1 and mailbox 0 go to the ARM. This means that these resources should be written by the GPU and read
by the ARM. The opposite holds for doorbells 2, 3 and mailbox 1.
The mailbox interface has 28 bits (MSB) available for the value and 4 bits (LSB) for the channel. Channels 8 and 9 are used:
- Channel 8: Request from ARM for response by VC.
- Channel 9: Request from VC for response by ARM (none currently defined) For ARM to VC properties, mailbox 1 is used to send the address of the message, which the VideoCore updates before sending the same address back on mailbox 0. For more information, refer to the resources.
RPi4
The mailbox interface for the RPi4 has not changed since the BCM2837.
USB
Resources
- USB information: https://www.raspberrypi.org/documentation/hardware/raspberrypi/usb/README.md
- USB bandwidth: https://raspberrypi.stackexchange.com/questions/22685/usb-bandwidth-for-the-rpi-model-b
RPi3
The RPi3 offers 4 x USB2.0 ports. The USB ports enable the attachment of peripherals such as keyboards, mice, webcams that provide the Pi with additional functionality. In all models prior to the Pi 4, the USB ports connect to a combo hub/Ethernet chip, which is itself a USB device connected to the single upstream USB port on BCM2835. A usb 2.0 bus can handle up to 480Mbits/s of bandwidth - a significant portion of that will be consumed by the overhead due to managing multiple devices, with exact numbers being hard to find, as they depend on each individual connected device, as well as what it is doing and how that is prioritized, but under worst-case scenarios can be up to 50%.
RPi4
On the Pi 4, the USB hub chip is connected to the SoC using a PCIe bus. For the Pi 4, a fully-featured host controller drives the
downstream USB ports. Downstream USB is provided by a Via Labs VL805 chip - that supports two USB 2.0 ports and two USB 3.0 ports.
This is connected to the BCM2711 SoC using a PCIe link, which is extremely fast. Therefore, the Pi 4 does not have the same speed
constraints of previous models, which means very fast data transfer rates, especially when using the USB 3.0 ports.
All four USB ports on the device are connected to the USB 2.0 hub, whilst the USB 3.0 ports (blue) are ALSO connected to the USB 3.0
bus via the USB 3.0 specific pins in the socket. USB 3.0 devices are constrained only by the total bandwidth available over the PCIe link.
VideoCore
Resources
- VideoCore IV (VC 4): https://elinux.org/Raspberry_Pi_VideoCore_APIs
- VideoCore VI (VC 6): https://www.raspberrypi.org/forums/viewtopic.php?t=244519
- VideoCore document: https://web.archive.org/web/20160803202903/https://www.broadcom.com/docs/support/videocore/VideoCoreIV-AG100-R.pdf
- Linux Kernel: Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml
RPi3
The Raspberry Pi contains a Broadcom VideoCore IV GPU providing OpenGL ES 1.1, OpenGL ES 2.0, hardware-accelerated OpenVG 1.1, Open EGL, OpenMAX and 1080p30 H.264 high-profile decode. The VideoCore maps the ARM physical address space directly to the bus address space seen by VideoCore.
RPi4
The VC6 is clearly derived from VC4, but it is significantly different. VC6 is only a slight extension over VC5.
UART
RPi3
- Linux Kernel: Documentation/devicetree/bindings/serial/brcm,bcm2835-aux-uart.txt
The BCM2837 SoC has two UARTS: a) 1 x PL011 UART (UART 0) and b) 1 x mini UART (UART 1).
a) PL011 UART (UART 0)
- Compatible: brcm,bcm2835-pl011 arm,pl011 arm,primecell
- Register address: 0x7e201000
- Register width: 0x200
- IRQ 25 (
VC_UART) of Bank 2 of interrupt-parent bcm2835-armctrl-ic
b) Mini UART (UART 1)
- Compatible: brcm,bcm2835-aux-uart
- Register address: 0x7e215040
- Register width: 0x40
- IRQ 29 (
AUX) of Bank 1 of interrupt-parent bcm2835-armctrl-ic
RPi4
The BCM2711 SoC has 6 UARTS: b) 5 x PL011 UARTs (UART0: 0x7e201000,UART2: 0x7e201400,UART3: 0x7e201600,UART4: 0x7e201800,UART5: 0x7e201a00) and b) 1 x mini UART (UART 1).
a) PL011 UARTs (UART 0, UART 2, UART 3, UART 4, UART 5)
- Compatible: arm,pl011 arm,primecell
UART 0:
- Register address: 0x7e201000
- Register width: 0x200
- IRQ: 96 + 57 = 153
UART 2:
- Register address: 0x7e201400
- Register width: 0x200
- IRQ: 96 + 57 = 153
UART 3:
- Register address: 0x7e201600
- Register width: 0x200
- IRQ: 96 + 57 = 153
UART 4:
- Register address: 0x7e201800
- Register width: 0x200
- IRQ: 96 + 57 = 153
UART 5:
- Register address: 0x7e201a00
- Register width: 0x200
- IRQ: 96 + 57 = 153
b) Mini UART (UART 1)
- Compatible: brcm,bcm2835-aux-uart
- Register address: 0x7e215040
- Register width: 0x40
- IRQ: 96 + 29 = 125
Interrupt Controller
Top-Level interrupt controller
- Linux Kernel: Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
RPi3
- Compatible: brcm,bcm2836-armctrl-ic
- Register address: 0x7e00b200
- Register width: 0x200
- IRQ 8 (
GPU_FAST) of interrupt-parent bcm2836-l1-intc
RPi4
- Compatible: arm,gic-400
- Register address: 0x40041000 (Distributor), 0x40042000(CPU interfaces), 0x40044000(Virtual interface control block), 0x40046000(Virtual CPU interfaces)
- Register width: 0x1000, 0x2000, 0x2000, 0x2000
- PPI IRQ: 16 + 9 = 25
The interrupt-controller on the RPi4 is the ARM GIC-400. More information on IRQs can be found in the IRQ table at the bottom of the Wiki page.
Per-CPU interrupt controller
- Linux Kernel: Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt
RPi3
- Compatible: brcm,bcm2836-l1-intc
- Register address: 0x40000000
- Register width: 0x100
RPi4
- Compatible: brcm,bcm2836-l1-intc
- Register address: 0x40000000
- Register width: 0x100
Timer
System Timer
- Linux Kernel: Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt
RPi3
- Compatible: brcm,bcm2835-system-timer
- Register address: 0x7e003000
- Register width: 0x1000
- IRQ 0 (
TIMER0), 1 (TIMER1), 2 (TIMER2), 3 (TIMER3) of Bank 1 of interrupt-parent bcm2835-armctrl-ic - Clock frequency: 1000000 (0xf4240)
RPi4
- Compatible: brcm,bcm2835-system-timer
- Register address: 0x7e003000
- Register width: 0x1000
- VC IRQ: 96 + 0, 96 + 1, 96 + 2, 96 + 3
- Clock frequency: 1000000 (0xf4240)
ARM Timer (SP804)
- Linux Kernel: Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
- Generic ARM timer: https://developer.arm.com/architectures/learn-the-architecture/generic-timer/single-page
RPi3
- Compatible: arm,armv7-timer
- IRQ 0 (
CNTPSIRQ), 1 (CNTPNSIRQ), 2 (CNTHPIRQ), 3 (CNTVIRQ) of interrupt-parent bcm2836-l1-intc
RPi4
- Compatible: arm,armv8-timer
- Register address: 0x7e00b000
- EL3 Physical Timer: 16 + 13 = 29
- EL1 Physical Timer: 16 + 14 = 30
- EL1 Virtual Timer: 16 + 11 = 27
- Non-secure EL2 Physical Timer: 16 + 10 = 26
SD
MMC
- Linux Kernel: Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhost.txt
RPi3
- Compatible: brcm,bcm2835-sdhost
- Register address: 0x7e202000
- Register width: 0x100
- IRQ 24 (
VC_SDIO) of Bank 2 of interrupt-parent bcm2835-armctrl-ic - Bus width: 4
RPi4
- Compatible: brcm,bcm2835-sdhost
- Register address: 0x7e202000
- Register width: 0x100
- IRQ: 96 + 56 = 152
EMMC
- Linux Kernel: Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
RPi3
- No entry in dts file
RPi4
- Compatible: brcm,bcm2711-emmc2
- Register address: 0x7e340000
- Register width: 0x100
- IRQ: 96 + 62 = 158 (EMMC & EMMC2)
SDHCI
- Linux Kernel: Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
- Linux Kernel: Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt
RPi3
- Compatible: brcm,bcm2835-sdhci
- Compatible (Wifi): brcm,bcm4329-fmac
- Register address: 0x7e300000
- Register width: 0x100
- IRQ 30 (
VC_ARASANSDIO) of Bank 2 of interrupt-parent bcm2835-armctrl-ic
RPi4
- Compatible: brcm,bcm2835-sdhci
- Compatible (Wifi): brcm,bcm4329-fmac
- Register address: 0x7e300000
- Register width: 0x100
- SPI IRQ: 96 + 62 = 158
SPI
RPi3
- Linux Kernel: Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt
- Linux Kernel: Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt
SPI 0
- Compatible: brcm,bcm2835-spi
- Register address: 0x7e204000
- Register width: 0x1000
- IRQ 22 (
VC_SPI) of Bank 2 of interrupt-parent bcm2835-armctrl-ic
AUX SPI 1
- Compatible: brcm,bcm2835-aux-spi
- Register address: 0x7e215080
- Register width: 0x40
- IRQ 29 (
AUX) of Bank 1 of interrupt-parent bcm2835-armctrl-ic
AUX SPI 2
- Compatible: brcm,bcm2835-aux-spi
- Register address: 0x7e2150c0
- Register width: 0x40
- IRQ 29 (
AUX) of Bank 1 of interrupt-parent bcm2835-armctrl-ic
RPi4
SPI 0,3,4,5,6
SPI0:
- Compatible: brcm,bcm2835-spi
- Register address: 0x7e204000
- Register width: 0x200
- SPI IRQ: 96 + 54 = 150
SPI3:
- Compatible: brcm,bcm2835-spi
- Register address: 0x7e204600
- Register width: 0x200
- SPI IRQ: 96 + 54 = 150
SPI4:
- Compatible: brcm,bcm2835-spi
- Register address: 0x7e204800
- Register width: 0x200
- SPI IRQ: 96 + 54 = 150
SPI5:
- Compatible: brcm,bcm2835-spi
- Register address: 0x7e204a00
- Register width: 0x200
- SPI IRQ: 96 + 54 = 150
SPI6:
- Compatible: brcm,bcm2835-spi
- Register address: 0x7e204c00
- Register width: 0x200
- SPI IRQ: 96 + 54 = 150
AUX SPI 1,2
AUX SPI 1:
- Compatible: brcm,bcm2835-aux-spi
- Register address: 0x7e215080
- Register width: 0x40
- IRQ: 96 + 29 = 125
AUX SPI 2:
- Compatible: brcm,bcm2835-aux-spi
- Register address: 0x7e2150c0
- Register width: 0x40
- IRQ: 96 + 29 = 125
USB
- Linux Kernel: Documentation/devicetree/bindings/usb/dwc2.yaml
RPi3
- Compatible: brcm,bcm2835-usb usb424,9514 usb424,ec00 (for ethernet)
- Register address: 0x7e980000
- Register width: 0x10000
- IRQ 9 (
VC_USB) of Bank 1 of interrupt-parent bcm2835-armctrl-ic
RPi4 (USB connected over PCIE)
- Compatible: brcm,bcm2835-usb
- Register address: 0x7e980000
- Register width: 0x10000
- IRQ: 96 + 9 = 105
Gigabit Ethernet (GENET)
- Linux Kernel: Documentation/devicetree/bindings/net/brcm,bcmgenet.txt
RPi3
- Ethernet connected over USB2.0 bus (see above)
RPi4
- Compatible: brcm,bcm2711-genet-v5
- Register address: 0x7d580000
- Register width: 0x10000
- IRQ: 160 + 29 = 189, 160 + 30 = 190
The first interrupt (189) is the general purpose interrupt line, while the second interrupt (190) is the interrupt for the ring RX and TX queues operating in ring mode.
HDMI
- Linux Kernel: Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml
RPi3
HDMI0
- Compatible: brcm,bcm2835-hdmi
- Register address: 0x7e902000, 0x7e808000
- Register width: 0x600, 0x100
- IRQ 8 (
HDMI0) and 9 (HDMI1) of Bank 2 of interrupt-parent bcm2835-armctrl-ic
RPi4
- Linux Kernel: Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
HDMI0
- Compatible: brcm,bcm2711-hdmi0
- Register address: 0x7ef00700, 0x7ef00300, 0x7ef00f00, 0x7ef00f80, 0x7ef01b00, 0x7ef01f00, 0x7ef00200, 0x7ef04300, 0x7ef20000
- Register width: 0x300, 0x200, 0x80, 0x80, 0x200, 0x400, 0x80, 0x100, 0x100
- IRQ: 96 + 40 = 136
HDMI1
- Compatible: brcm,bcm2711-hdmi1
- Register address: 0x7ef05700, 0x7ef05300, 0x7ef05f00, 0x7ef05f80, 0x7ef06b00, 0x7ef06f00, 0x7ef00280, 0x7ef09300, 0x7ef20000
- Register width: 0x300, 0x200, 0x80, 0x80, 0x200, 0x400, 0x80, 0x100, 0x100
- IRQ: 96 + 41 = 137
Broadcom Serial Controller - BSC / I2C
- Linux Kernel: Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.txt
RPi3
BSC0
- Compatible: brcm,bcm2835-i2c
- Register address: 0x7e205000
- Register width: 0x1000
- IRQ 21 (
VC_I2C) of Bank 2 of interrupt-parent bcm2835-armctrl-ic - clock frequency: 100000 Hz (0x186a0)
BSC1
- Compatible: brcm,bcm2835-i2c
- Register address: 0x7e804000
- Register width: 0x1000
- IRQ 21 (
VC_I2C) of Bank 2 of interrupt-parent bcm2835-armctrl-ic - clock frequency: 100000 Hz (0x186a0)
BSC2
- Compatible: brcm,bcm2835-i2c
- Register address: 0x7e805000
- Register width: 0x1000
- IRQ 21 (
VC_I2C) of Bank 2 of interrupt-parent bcm2835-armctrl-ic - clock frequency: 100000 Hz (0x186a0)
RPi4
- Linux Kernel: Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.txt
- Linux Kernel: Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml
BSC0
- Compatible: brcm,bcm2711-i2c brcm,bcm2835-i2c
- Register address: 0x7e205000
- Register width: 0x200
- IRQ: 96 + 53 = 149
- clock frequency: 100000 Hz (0x186a0)
BSC1
- Compatible: brcm,bcm2711-i2c brcm,bcm2835-i2c
- Register address: 0x7e804000
- Register width: 0x200
- IRQ: 96 + 53 = 149
- clock frequency: 100000 Hz (0x186a0)
BSC3
- Compatible: brcm,bcm2711-i2c brcm,bcm2835-i2c
- Register address: 0x7e205600
- Register width: 0x200
- IRQ: 96 + 53 = 149
- clock frequency: 100000 Hz (0x186a0)
BSC4
- Compatible: brcm,bcm2711-i2c brcm,bcm2835-i2c
- Register address: 7e205800
- Register width: 0x200
- IRQ: 96 + 53 = 149
- clock frequency: 100000 Hz (0x186a0)
BSC5
- Compatible: brcm,bcm2711-i2c brcm,bcm2835-i2c
- Register address: 0x7e205a00
- Register width: 0x200
- IRQ: 96 + 53 = 149
- clock frequency: 100000 Hz (0x186a0)
BSC6
- Compatible: brcm,bcm2711-i2c brcm,bcm2835-i2c
- Register address: 0x7e205c00
- Register width: 0x200
- IRQ: 96 + 53 = 149
- clock frequency: 100000 Hz (0x186a0)
BSC2 (used by HDMI interface)
- Caution: should not be accessed by user program
- Compatible: brcm,bcm2711-hdmi-i2c
- Register address: 0x7ef04500, 0x7ef00b00
- Register width: 0x100, 0x300
- clock frequency: 97500 Hz (0x17cdc)
BSC7 (used by HDMI interface)
- Caution: should not be accessed by user program
- Compatible: brcm,bcm2711-hdmi-i2c
- Register address: 0x7ef09500, 0x7ef05b00
- Register width: 0x100, 0x300
- clock frequency: 97500 Hz (0x17cdc)
PCIE
- Linux Kernel: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
RPi3
- No entry in dts file for PCIE
RPi4
- Compatible: brcm,bcm2711-pcie
- Register address: 0x7d500000
- Register width: 0x9310
- IRQ: 160 + 20 = 180
Watchdog
- Linux Kernel: Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt
- Linux Kernel: Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.txt
RPi3
- Compatible: brcm,bcm2835-pm-wdt
- Register address: 0x7e100000
- Register width: 0x28
RPi4
- Compatible: brcm,bcm2835-pm brcm,bcm2835-pm-wdt
- Register address: 0x7e100000, 0x7e00a000, 0x7ec11000
- Register width: 0x114, 0x24, 0x20
GPIO
- Linux Kernel: Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt
RPi3
- Compatible: brcm,bcm2835-gpio
- Register addresss: 0x7e200000
- Register width: 0xb4
- IRQ 17 (
GPIO0), 18 (GPIO1), 19 (GPIO2), 20 (GPIO3) of Bank 2 of interrupt-parent bcm2835-armctrl-ic
RPi4
- Compatible: brcm,bcm2711-gpio
- Register address: 0x7e200000
- Register width: 0xb4
- VC IRQ: 96 + 49 = 145,...,96 + 52 = 148
Mailbox
Broadcom BCM2835 VideoCore mailbox IPC
RPi3
- Compatible: brcm,bcm2835-mbox
- Register address: 0x7e00b880
- Register width: 0x40
- IRQ 1 (
ARM_MAILBOX) of Bank 0 of interrupt-parent bcm2835-armctrl-ic
RPi4
- Compatible: brcm,bcm2835-mbox
- Register address: 0x7e00b880
- Register width: 0x40
- SPI IRQ: 64 + 1 = 65
Broadcom VCHIQ firmware services
- Linux Kernel: Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt
RPi3
- Compatible: brcm,bcm2835-vchiqa
- Register address: 0x7e00b840
- Register width: 0x0f
- IRQ 2 (
ARM_DOORBELL_0) of Bank 0 of interrupt-parent bcm2835-armctrl-ic
RPi4
- Compatible: brcm,bcm2835-vchiqa
- Register address: 0x7e00b840
- Register width: 0x3c
- SPI IRQ: 64 + 2 = 66
Pulse-Width Modulation (PWM)
- Linux Kernel: Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt
RPi3
- Compatible: brcm,bcm2835-pwm
- Register address: 0x7e20c000
- Register width: 0x28
RPi4
PWM0
- Compatible: brcm,bcm2835-pwm
- Register address: 0x7e20c000
- Register width: 0x28
PWM1
- Compatible: brcm,bcm2835-pwm
- Register address: 0x7e20c800
- Register width: 0x28
Random Number Generator (RNG)
- Linux Kernel: Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt
- Linux Kernel: Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml
RPi3
- Compatible: brcm,bcm2835-rng
- Register address: 0x7e104000
- Register width: 0x10
- IRQ 29 (
RNG) of Bank 2 of interrupt-parent bcm2835-armctrl-ic
RPi4
- Compatible: brcm,bcm2711-rng200
- Register address: 0x7e104000
- Register width: 0x28
Reset
- Linux Kernel: Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
Memory
RPi3
- Hard-coded for 1GiB (0x40000000)
RPi4
- RAM size not specified in dts file -> needs to be specified in overlay dts file by the user
PMU (Power Management Unit)
- Linux Kernel: Documentation/devicetree/bindings/arm/pmu.yaml
RPi3
- Compatible: arm,cortex-a53-pmu
- IRQ 9 (
PMU_FAST) of interrupt-parent bcm2836-l1-intc
RPi4
- Compatible: arm,cortex-a72-pmu arm,armv8-pmuv3
- IRQ: 16,17,18,19 (one for each core)
DMA
- Linux Kernel: Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
RPi3
- Compatible: brcm,bcm2835-dma
- Register address: 0x7e007000
- Register width: 0xf00
- IRQ 16 (
DMA0), 17 (DMA1), 18 (VC_DMA2), 19 (VC_DMA2),..., 26 (DMA10), 27 (DMA11-14), 28 (DMAALL) of Bank 1 of interrupt-parent bcm2835-armctrl-ic
RPi4
- Compatible: brcm,bcm2835-dma
- Register address: 0x7e007000
- Register width: 0xb00
- VC IRQ: 96 + 16 = 112,..., 96 + 28 = 124
Clock
RPi3
- Compatible: simple-bus fixed-clock
Oscillator (OSC)
- Clock frequency: 19200000 Hz (0x124f800)
USB clock (OTG)
- Clock frequency: 480000000 Hz (0x1c9c3800)
RPi4
- Linux Kernel Documentation/devicetree/bindings/clock/brcm,bcm2711-dvp.yaml
Oscillator (OSC)
- Clock frequency: 54000000 Hz (0x337f980)
USB clock
- Clock frequency: 480000000 Hz (0x1c9c3800)
HDMI clock
- Register address: 0x7ef00000
- Register width: 0x10
27MHz clock
- Clock frequency: 27000000 Hz (0x19bfcc0)
108MHz clock
- Clock frequency: 108000000 Hz (0x66ff300)
IRQ table - GIC-400
According to https://stackoverflow.com/questions/27709349/what-is-the-difference-between-ppi-spi-and-sgi-interrupts, there are the following
interrupts in ARM:
IRQ 0 - 15: Software Generated Interrupts (SGI) - software interrupt for inter-core communication
IRQ 16 - 31: Private Peripheral Interrupts (PPI) - hardware interrupt private to a core
| IRQ | RPi3 | RPi4 |
|---|---|---|
| 19 | Secure EL2 Virtual Timer (CNTHVS) | |
| 20 | Secure EL2 Physical Timer (CNTHPS) | |
| 26 | Non-secure EL2 Physical Timer (CNTHP) | |
| 27 | EL1 Virtual Timer (CNTV) | |
| 28 | Non-secure EL2 Virtual Timer (CNTHV) | |
| 29 | EL3 Physical Timer (CNTPS) | |
| 30 | EL1 Physical Timer (CNTP) | |
| 31 | Legacy IRQ |
More information on the Generic Timers of the ARMv8-a architecture can be seen in: https://developer.arm.com/documentation/102379/0000/The-processor-timers?lang=en.
IRQ 32 - 216: Shared Peripheral Interrupts (SPI) - hardware interrupt that the interrupt controller can route to more than one core
| IRQ | RPi3 | RPi4 |
|---|---|---|
| 32-47 | ARM Mailbox IRQs | |
| 48 | Core 0 PMU IRQ | |
| 49 | Core 1 PMU IRQ | |
| 50 | Core 2 PMU IRQ | |
| 51 | Core 3 PMU IRQ | |
| 53 | Local timer IRQ | |
| 64-79 | ARMC peripheral IRQs | |
| 96-159 | VC peripheral IRQs | |
| 160-216 | ETH_PCIe L2 IRQs |
ARMC peripheral IRQs (64-79)
| IRQ | RPi3 | RPi4 |
|---|---|---|
| 64 (0) | ARM Timer (SP804) | |
| 65 (1) | ARM Mailbox | |
| 66 (2) | Doorbell 0 | |
| 67 (3) | Doorbell 1 | |
| 68 (4) | VPU0 halted | |
| 69 (5) | VPU1 halted | |
| 70 (6) | ARM address error | |
| 71 (7) | ARM AXI error | |
| 72-79 (8-15) | Software interrupt |
VC peripheral IRQs (96-159)
| IRQ | RPi3 | RPi4 |
|---|---|---|
| 96 (0) | Timer 0 | |
| 97 (1) | Timer 1 | |
| 98 (2) | Timer 2 | |
| 99 (3) | Timer 3 | |
| 100 (4) | H264 0 | |
| 101 (5) | H264 1 | |
| 102 (6) | H264 2 | |
| 103 (7) | JPEG | |
| 104 (8) | ISP | |
| 105 (9) | USB | |
| 106 (10) | V3D | |
| 107 (11) | Transposer | |
| 108 (12) | Multicore Sync 0 | |
| 109 (13) | Multicore Sync 1 | |
| 110 (14) | Multicore Sync 2 | |
| 111 (15) | Multicore Sync 3 | |
| 112 (16) | DMA 0 | |
| 113 (17) | DMA 1 | |
| 114 (18) | DMA 2 | |
| 115 (19) | DMA 3 | |
| 116 (20) | DMA 4 | |
| 117 (21) | DMA 5 | |
| 118 (22) | DMA 6 | |
| 119 (23) | DMA 7 & 8 | |
| 120 (24) | DMA 9 & 10 | |
| 121 (25) | DMA 11 | |
| 122 (26) | DMA 12 | |
| 123 (27) | DMA 13 | |
| 124 (28) | DMA 14 | |
| 125 (29) | AUX | |
| 126 (30) | ARM | |
| 127 (31) | DMA 15 | |
| 128 (32) | HDMI CEC | |
| 129 (33) | HVS | |
| 130 (34) | RPIVID | |
| 131 (35) | SDC | |
| 132 (36) | DSI 0 | |
| 133 (37) | Pixel Valve 2 | |
| 134 (38) | Camera 0 | |
| 135 (39) | Camera 1 | |
| 136 (40) | HDMI 0 | |
| 137 (41) | HDMI 1 | |
| 138 (42) | Pixel Valve 3 | |
| 139 (43) | SPI/BSC Slave | |
| 140 (44) | DSI 1 | |
| 141 (45) | Pixel Valve 0 | |
| 142 (46) | Pixel Valve 1 & 4 | |
| 143 (47) | CPR | |
| 144 (48) | SMI | |
| 145 (49) | GPIO 0 | |
| 146 (50) | GPIO 1 | |
| 147 (51) | GPIO 2 | |
| 148 (52) | GPIO 3 | |
| 149 (53) | OR of all I2C | |
| 150 (54) | OR of all SPI | |
| 151 (55) | PCM/I2S | |
| 152 (56) | SDHOST | |
| 153 (57) | OR of all PL011 UART | |
| 154 (58) | OR of all ETH_PCIe L2 | |
| 155 (59) | VEC | |
| 156 (60) | CPG | |
| 157 (61) | RNG | |
| 158 (62) | EMMC & EMMC2 | |
| 159 (63) | ETH_PCIe secure |
ETH_PCIe L2 IRQs (160-216)
| IRQ | RPi3 | RPi4 |
|---|---|---|
| 169 (9) | AVS | |
| 175 (15) | PCIE_0_INTA | |
| 176 (16) | PCIE_0_INTB | |
| 177 (17) | PCIE_0_INTC | |
| 178 (18) | PCIE_0_INTD | |
| 180 (20) | PCIE_0_MSI | |
| 189 (29) | GENET_0_A | |
| 190 (30) | GENET_0_B | |
| 208 (48) | USB0_XHCI_0 |
More on Interrupt Controllers
The BCM2711 has a choice of two interrupt controllers: the GIC-400 interrupt
controller and the legacy interrupt controller. It is possible to switch between
the two interrupt controller via the enable_gic flag in config.txt.
Interrupt Sources and Destinations
In the following diagram, the orange boxes illustrate the various interrupt
source blocks, the blue box covers the interrupt controller routing and the
green box shows the final interrupt destinations:
The ARM Core n source (orange) and destination (green) blocks are the same
cores. ARM_LOCAL and ARMC are different hardware blocks within the chip.
ARMC is visible to both the VPU and CPU, but ARM_LOCAL is only visible to
the CPU.
The final output from each interrupt controller is 8 separate signals - a FIQ
(Fast interrupt request) and an IRQ for each of the 4 ARM cores. FIQn and
IRQn are connected to core n.
VideoCore (VC) interrupts
There exist 64 VideoCore interrupts on the BCM2711 that are offset with a 64
base IRQ. Because there are more peripherals than available VC IRQs, some of the
VC peripheral interrupts are the OR-ed version of multiple peripheral interrupts
as can be seen in the following diagram:
The per-peripheral interrupt statuses for VC peripheral IRQs 29, 53, 54 and 57
can be read from the AUX_IRQ (0x7e215000) and PACTL_CS (0x7e204e00)
registers. The vertically aligned numbers 0-20 indicate the bit-positions within
the registers. The other way to know which peripheral has issued the interrupt
is to check the IRQ pending bit in the corresponding status register of the
peripheral.
For peripherals corresponding to VC peripheral interrupts 23, 24, 46 and 62,
checking the status registers is the only way to find out which of the two
peripherals issued the IRQ.
GIC-400
The BCM2711 contains an ARM GIC-400 interrupt controller that is enabled by
default. The following diagram shows how the interrupt sources are connected to
the GIC:
Even when the GIC-400 is selected as the interrupt controller, the outputs of
the legacy interrupt controller are available as PPIs within the GIC.
When the GIC-400 is selected, the FIQn/IRQn from the GIC-400 are forwarded
to the ARM core FIQn/IRQn.
For more information on the GIC-400, refer to the BCM2711 TRM.
Legacy Interrupt Controller
The legacy interrupt controller in the BCM2711 has some similarities with the
interrupt controllers used in earlier BCM283x chips but also several differences.
When the legacy interrupt controller is selected, the legacy FIQn/IRQn outputs
are routed to the FIQn/IRQn inputs of the ARM cores.
For more information on the legacy interrupt controller, refer to the BCM2711
TRM.
ARMv8-A Exception Levels
- Resource: https://medium.com/@om.nara/aarch64-exception-levels-60d3a74280e6
- Resource: https://developer.arm.com/architectures/learn-the-architecture/exception-model/privilege-and-exception-levels
There are 4 different exception levels in ARMv8 architecture which represent different software execution privileges.
- EL0: Applications
- EL1: OS kernel and associated functions that are typically described as privileged (Rich OS)
- EL2: Hypervisor
- EL3: Firmware, Secure Monitor
Privilege ordering: EL0 < EL1 < EL2 < EL3
Memory System
L0 Memory System (Registers)
- Cortex A-72: https://developer.arm.com/documentation/100095/0003/programmers-model/armv8-a-architecture-concepts/execution-state
- Cortex A-53: https://developer.arm.com/documentation/ddi0500/e/programmers-model/armv8-a-architecture-concepts/execution-state?lang=en
As both CPUs feature the ARMv8-A architecture, the following information holds for Cortex-A53 (RPi3) as well as for Cortex-A72 (RPi4):
AARCH32 - The 32-bit Execution state:
- AARCH32 is backwards-compatible with implementations of the ARMv7-A architecture profile that include the Security Extensions and the Virtualization Extensions
- 13 32-bit general purpose registers
- 32-bit PC, SP, and Link Register (LR)
- 32 64-bit registers for Advanced SIMD and Floating-point support
- Provides two instruction sets: A32 and T32
- Provides an exception model that maps the ARMv7 exception model onto the ARMv8 exception model and Exception levels
- Features 32-bit VAs. The VMSA maps these to 40-bit PAs.
- Collects processor state into the Current Processor State Register (CPSR)
AARCH64 - The 64-bit Execution state:
- 31 64-bit general-purpose registers
- 64-bit Program Counter (PC), Stack Pointer (SP), and Exception Link Registers (ELRs)
- Provides a single instruction set: A64
- ARMv8 exception model: EL0-EL3
- 48-bit Virtual Address (VA), held in 64-bit registers. The Cortex-A72 processor VMSA maps these to 44-bit Physical Address (PA) maps. The Cortex-A53 VMSA implementation maps these to 40-bit Physical Address (PA) maps.
The processor can move between Execution states only on a change of Exception level. This means different software layers, such as an application, an operating system kernel, and a hypervisor, executing at different Exception levels, can execute in different Execution states.
L1 Memory System (L1 Cache)
- RPi3: https://www.raspberrypi.org/forums/viewtopic.php?t=145811
- Cortex A-53: https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system/about-the-l1-memory-system?lang=en
- RPi4: https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md
- Cortex A-72: https://developer.arm.com/documentation/100095/0003/level-1-memory-system/about-the-l1-memory-system
Cortex A-53 (RPi3)
The L1 memory system consists of separate instruction and data caches.
The L1 Instruction memory system has the following key features:
- Instruction side cache line length of 64 bytes.
- 2-way set associative L1 Instruction cache.
- 128-bit read interface to the L2 memory system.
The L1 Data memory system has the following features:
- Data side cache line length of 64 bytes.
- 4-way set associative L1 Data cache.
- 256-bit write interface to the L2 memory system.
- 128-bit read interface to the L2 memory system.
You cannot disable the L2 and L1 Data caches independently, because they are controlled by the same enable.
The implementer configures the instruction and data caches independently during implementation, to sizes of 8KB, 16KB, 32KB, or 64KB. On the RPi3 there are 16KB L1 I-Cache and 16KB L1 D-Cache.
Cortex A-72 (RPi4)
The L1 memory system consists of separate instruction and data caches.
The L1 instruction memory system has the following features:
- 48KB 3-way set-associative instruction cache.
- Fixed line length of 64 bytes.
- Instruction cache that behaves as Physically-indexed and physically-tagged (PIPT).
- Least Recently Used (LRU) cache replacement policy.
The L1 data memory system has the following features:
- 32KB 2-way set-associative data cache.
- Fixed line length of 64 bytes.
- Data cache that is PIPT.
- Out-of-order, speculative, non-blocking load requests to Normal memory and non-speculative, non-blocking load requests to Device memory.
- LRU cache replacement policy.
The Cortex-A72 processor does not support cache lockdown.
You can disable each cache independently.
On the RPi4 there are 48 KB L1 I-Cache and 32 KB L1 D-Cache.
L2 Memory System (L2 Cache)
- RPi3: https://www.raspberrypi.org/forums/viewtopic.php?t=145811
- Cortex A-53: https://developer.arm.com/documentation/ddi0500/e/level-2-memory-system/about-the-l2-memory-system
- RPi4: https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md
- Cortex A-72: https://developer.arm.com/documentation/100095/0003/level-2-memory-system/about-the-l2-memory-system
Cortex A-53 (RPi3)
Integrated Snoop Control Unit (SCU), connecting up to four cores within a cluster. The L2 memory system interfaces to the external memory system with either an AMBA 4 ACE bus or an AMBA 5 CHI bus. All bus interfaces are 128-bits wide.
Optional tightly-coupled L2 cache that includes:
- Fixed line length of 64 bytes.
- Physically indexed and tagged cache.
- 16-way set-associative cache structure.
Configurable L2 cache size of 128KB, 256KB, 512KB, 1MB and 2MB. On the RPi3 there is 512 KB L2 Cache.
Cortex A-72 (RPi4)
The L2 memory system consists of a tightly-coupled L2 cache and an integrated Snoop Control Unit (SCU), connecting up to four cores within a cluster and a configurable coherent external interface supporting AMBA4 (ACE) or CHI architectures.
The features of the L2 memory system include:
- Fixed line length of 64 bytes.
- Physically indexed and tagged cache.
- 16-way set-associative cache structure.
- Banked pipeline structures.
- Inclusion property with L1 data caches.
- Software-programmable pseudo-least-recently-used or pseudo-random cache-replacement policy.
The Cortex-A72 processor does not support TLB or cache lockdown.
Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB. On the RPi4 there is 1MB L2 Cache.
L2 Cache Controller
The cache controller is a hardware block responsible for managing the cache memory, in a way that is largely invisible to the program.
It automatically writes code or data from main memory into the cache. It takes read and write memory requests from the core and performs
the necessary actions to the cache memory or the external memory. (https://developer.arm.com/documentation/den0024/a/Caches/Cache-controller)
Level 2 cache controllers improve processor performance by keeping memory access on-chip. Level 2 cache controllers also contribute
significantly to power efficiency because on-chip accesses are typically lower in power when compared to going off-chip. The level 2 cache
controllers are designed alongside the processor to match the processor requirements and easily integrate into AMBA AXI or AHB interconnects.
There are two types of cache controllers, the internal and the external cache controllers. The latter ones usually need to be controlled by
code.(https://developer.arm.com/ip-products/system-ip/system-controllers/cache-controllers)
A rather popular choice for an external L2 cache controller is the CoreLink L2C-310 cache controller (https://developer.arm.com/documentation/ddi0246/h/introduction/about-the-corelink-level-2-cache-controller-l2c-310).
It is a high-performance, AXI level 2 cache controller that is designed and optimized to address Arm processors that have an
AXI system interface. The following processors include the L2C-310 cache controller:
- Cortex-A5/-A9 processor,
- Cortex-R4/-R5/-R7 processor
The CoreLink L2C-310 cache controller supports cache lockdown (https://developer.arm.com/documentation/ddi0246/h/functional-overview/cache-operation/cache-lockdown), thus this cache controller can only be used when the processor actually supports cache lockdown. ARMv8 supports the cache lockdown feature, but it is implementation defined. This means only some of the Cortex-A processors support cache lockdown and L2C-310 cache controller. In fact all of the recent Cortex-A family cores (Cortex-A53/-A72) have an integrated L2 cache and therefore no need for an external L2 cache controller. They also don't support cache locking.(https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/3028/does-armv8-soc-support-cache-lockdown)
L3 Memory System (RAM)
The RPi3 holds 1GB LPDDR2. The RPi4 holds a configurable amount of RAM (1,2,4 or 8 GB LPDDR4).
L4 Memory System (Disk)
Independent of platform.