release notes 17 06 22 - lu-ping/chisel3 GitHub Wiki

Release Notes 06/22/17

Chisel3

• Fix a small typo in the README Chisel PR (#627)
• Add dontTouch for annotating Data to not be removed Chisel PR (#620)
• Dont try to instantiate firrtl.Transform from Annotation Chisel PR (#620)

Firrtl

• Add --no-dce command-line option to skip DCE Firrtl PR (#610)
• Replace IsInvalids on LowForm with connection to zero Firrtl PR (#605)
• Canonicalize spacing in RemoveValidIf Firrtl PR (#605)
• Make ExpandWhens delete 'is invalid' for attached Analog components Firrtl PR (#606)
• Style changes to ExpandWhensSpec Firrtl PR (#607)
• Add option to disable combinational loop detection Firrtl PR (#604)
• Move CheckCombLoops from passes/ to transforms/ Firrtl PR (#604)
• Change CheckCombLoops to a Transform Firrtl PR (#604)
• Fixes a typo in the verilog elsif code generation Firrtl PR (#603)
• Update travis button for new organization Firrtl PR (#602)
• Display the total time firrtl took to compile Firrtl PR (#599)
• Change base of randomization values to _RAND instead of _GEN Firrtl PR (#595)
• Add some comments to endif Firrtl PR (#595)

Chisel-testers

• bump versions; replace PropertyCheckConfig with PropertyCheckConfiguration Chisel-testers PR (#144)
• Fix double elaboration of DUT when using the interpreter Chisel-testers PR (#154)
• Update deprecated usage. Chisel-testers PR (#149)
• cancel AccumBlackBox_PeekPokeTest_VCS test if no vcs Chisel-testers PR (#152)
• This adds two examples of creating black box implementations Chisel-testers PR (#151)

Interpreter

• Prepare for Scala 2.12 - bump versions and replace deprecated usage. Firrtl-interpreter PR (#80)