9 How to init LCD and draw lines - limingth/LASO GitHub Wiki

LCD pin mux function as LCD signals

GPF0[7:0] : 0x22222222
GPF1[7:0] : 0x22222222
GPF2[7:0] : 0x22222222
GPF3[7:0] : 0x22222222

LCD clock

CLK_SRC0, R/W, Address = 0xE010_0200
Mux_DSYS: CLK_SRC0, 0xe0100200: 10001111 [20]=> 0
	MUX_DSYS_SEL  [20]  Control MUX_DSYS (0:SCLKMPLL, 1:SCLKA2M)  0  

MPLL: MPLL_CON: 0xa29b0c01 => 667Mhz (p358)
	Equation to calculate the output frequency:
	FOUT = MDIV X FIN / (PDIV X 2^SDIV)
	Fout = (0x29b)*24M/(12 * 2^1) = 667Mhz

HCLK_DSYS_RATIO  [19:16]  DIVHCLKD clock divider ratio, 
	HCLK_DSYS = MOUT_DSYS / (HCLK_DSYS_RATIO + 1) 	
CLK_DIV0	Address = 0xE0100300: 0x14131440 -> [19:16] = 3
	HCLK_DSYS = 667M / (3+1) = 166Mhz

LCD pixel clock

LCD2 connector PIN30 
	XpwmTOUT1 [1] GPE0/TOUT1 30
S5PV210 pdf Page100
	XpwmTOUT[1]  GPD0[1]  TOUT_1 
S5PV210 pdf Page143
	Port Group GPD0 Control Register (GPD0CON, R/W, Address = 0xE020_00A0)
	GPD0CON[1]   [7:4]   
		0000 = Input     
		0001 = Output 
		0010 = TOUT_1 
		0011 ~ 1110 = Reserved 
		1111 = GPD0_INT[1] 

LCD SFRs function

DISPLAY_CONTROL - Display path selection (RGB=FIMD)
VIDCON0 - Enable the video output and the Display control signal. 
	- Determine the rates of VCLK
	- Selects the clock source and Determines the rates of VCLK 
VIDCON1 - Specifies the HSYNC/VSYNC pulse polarity
VIDTCON2 - LINEVAL & HOZVAL
WINCON0 - Enable the video output and the VIDEO control signal
VIDOSD0A - left top pixel (0, 0)
VIDOSD0B - right bottom pixel (479, 271)
VIDW00ADD0B0 - fb address
VIDW00ADD1B0 - fb address + fb size
VIDTCON0 - VBPD/VFPD/VSPW
VIDTCON1 - HBPD/HFPD/HSPW
SHADOWCON - Enables Channel 0