The Low Pin Count Bus

The LPC bus was ratified by Intel ye'old 1998 as a software emulation of the aging ISA bus found on eariler PC-compat machines. The LPC bus is a 4-bit wide multiplexed bus with a clock of 33.3MHz for both address and data. The LPC bus has physically seven signals bus lines and since no connectors are defined as the topology of things on the bus are specific to the mainboard no device discovery is supported.

The LPC bus requires a minimum of seven signals, LAD[3:0] is comprise of four data line, while the other three are control signals. In particular, LFRAME# indicates the start of a new cycle or termination of a broken cycle, LRESET# provides the same type of function as the PCI reset signal, and LCLK is the 33MHz clock.

Optionally there are sideband signals that convey power management and interrupts; The LDRQ# is defined to suport DMA operations while SERIRQ allows peripherals to generate an interrupt if the host does not have ISA-based IRQ lines as iterrupt inputs.

Vendors such as SMSC, Winbond and Fintek are common providers of devices known as Super I/O's an Embedded Controllers. These devices provide a full complement of common legacy I/O peripherals such as, UARTs, parallel ports, PS2 mouse & kb.

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CLKRUN#, LPME#, LPCPD#, LSMI#

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