IntelRegistersTodo - larcenists/larceny GitHub Wiki

The current register asssignment on Larceny's Intel targets:

    GLOBALS   esp
    CONT      ebp
    TEMP      eax == SECOND
    RESULT    ebx
    REG1      ecx  (ecx must map to VM register)
    REG2      edx
    REG3      edi  (edi must map to VM register)
    REG0      esi (IAssassin, peephole branch) == REG4 (NASM, IAssassin trunk)

PnkFelix thinks we don't have much chance of freeing any of these registers up to be REGn (where n is 4 or 5...).

• GLOBALS is our point of reference for everything
• RESULT is used too much to be anywhere else.
• It would be interesting/insane to make CONT, the stack cache pointer, an entry in the globals array.
  • Slow down all stack accesses by an incredible amount to free up one hardware register...
  • Lars was willing to do this for reg0, which meant all constant vector accesses, lexical accesses, and code invocations took a hit...
  • Should we at least measure the effect?
• PnkFelix considered trying to remove TEMP, but even if its possible, the machinations are pretty ridiculous.

• Check whether making reg0 a hardware register is actually a win after all the peepholes are in

  • (The peepholes tend to only take effect when you use hardware register for your operations, so making reg4 a hardware register may be better after all.)
  • But PnkFelix is pretty skeptical about this.

• Try making RESULT be %eax and TEMP be %ebx, instead of the other way around.

  • Lars has occasional notes on where this would have been a win.
    • PnkFelix thinks the key to making this an actual win will be to find as many places as possible where we could use RESULT in place of TEMP, for code size.
  • This requires coordination between the code generator and the runtime, because TEMP will still have to be SECOND for mcode calls, so the millicode interface changes.