The nanoPU Artifact Documentation

The nanoPU is a new NIC-CPU co-design to minimize latency of the host network stack. It achieves its goal by providing a fast path between the network and applications, which has the following characteristics: (1) it moves key resource scheduling decisions from software to hardware (reliable network transport & congestion control, RPC load balancing across cores, thread scheduling) allowing them to operate much more efficiently, and (2) it provides a path directly between the network and applications which bypasses the cache and memory hierarchy placing arriving messages directly into the CPU register file.

We built an FPGA prototype of the nanoPU fast path using the Chipyard development environment and evaluated it using a combination of cycle-accurate software simulations with Verilator and cycle-accurate AWS FPGA-accelerated simulations with Firesim.

This wiki provides an overview of the nanoPU source code repositories as well as detailed instructions to reproduce the results presented in our OSDI paper. In order to facilitate reproducibility, we have developed a custom AWS EC2 image with all the necessary tools and repositories pre-installed. We hope this artifact will provide a useful starting point for other researchers to build upon the nanoPU. See the following pages for additional documentation:

• Repository Overview
• AWS Setup Instructions
• Verilator Simulations
• Firesim Simulations