Timing Verification - kkanthan77/Static-Timing-Analysis GitHub Wiki

Timing checks that are actively performed

Both these checks are performed at multiple conditions including worst-case slow condition and best-case fast condition.
For setup check, 'worst-case-slow' condition is critical.
For hold check, 'best-case-fast' condition is critical.

This ensures that the data is available at the input of the flip-flop before it is clocked in the flip-flop.
The data should be stable, for a certain amount of time, namely, setup time of the flip flop, before the active edge of the clock arrives at the flip-flop.
The setup check is from the first active edge of the clock in the launch flip-flop to the closest following active edge of the capture flip-flop.
The setup check ensures that the data launched from the previous clock cycle is ready to be captured after one cycle.

Tlaunch+Tclktoq+Tdp < Tcapture + Tcycle - Tsetup

The total time it takes for the data to arrive at the D pin of the capture flip-flop must be less than the time it takes for the clock to travel to the capture flip-flop plus a clock cycle delay minus the setup time.
Since the setup check poses a max constraint, the setup check always uses the longest or the max timing path.
This check is normally verified at the slow corner where the delays are the largest.

If it is set ideal in the report, it indicates that the clock trees are treated as ideal, that any buffers in the clock path are assumed to have zero delay.
Once the clock trees are built, the clock network can be marked as propagated.

It is calculated by set_input_transition command.
If this is not specified, ideal slew is assumed, both rise and fall transition times are 0ns.

This is also called as Insertion delay.
This is the time it takes for a clock to propagate from its source to the clock definition point of the design under analysis.

set_clock_latency -source -rise 0.7 [get_clocks CLK]

This is the latency from the clock definition point in the DUA to the clock pin of a flip-flop.
Clock network latency is used to model the delay through the clock path before the clock trees are built, that is prior to CTS.
Once a clock tree is marked as propagated, this clock network latency is ignored.

If one were to plot a frequency histogram of setup slack versus number of paths for a typical design, it would look like the one shown in Figure.

Zero slack line would be more towards right for an un optimized design and more towards left for an optimized design.
For a design that has zero violations, that is no paths with negative slack, the entire curve would be to the right of the zero slack line.

This ensures that a flip-flop output value that is changing does not pass through to a capture flip-flop and overwrite its output before the flip-flop has had a chance to capture its original value.
The hold specification of a flip-flop requires that the data being latched should be held stable for a specified amount of time after the active edge of the clock.

Hold check is from one active edge of the clock in the launch flip-flop to the same clock edge at the capture flip-flop.
Hold check ensures that the intended data in the capture flip-flop is not overwritten.
Data arrival time and clock arrival time at capture flip-flop must be larger than the hold time of the capture flip-flop, so that, the previous data on the flip-flop is not overridden and the data is reliably captured in the flip-flop.

Tlaunch_Tcq+Tdp > Tcapture + Thold

Hold checks are always verified using the shortest paths. Thus, the hold checks are typically performed at the fast timing corner.

Data from the subsequent launch edge must not be captured by the setup receiving edge.
Data from the setup launch edge must not be captured by the preceding receiving edge.

Setup check is between setup launch edge and setup receiving edge.
The subsequent launch edge must not propagate data so fast that the setup receiving edge does not have time to capture its data reliably.
The setup launch edge must not propagate data so fast that the preceding receiving edge does not get a chance to capture its data.

If combinatioinal data path between two flip-flops can take more that one clock cycle to propagate through the logic, then it is a multicycle path.
Even though the data is being captured by the capture flip-flop on every clock edge, we direct STA that the relevant capture edge occurs after specified number of clock cycles.

create_clock -name CLKM -period 10 [get_ports CLKM] set_multicycle_path 3 -setup

This ensures that the design utilizes the required data only every third cycle instead of every cycle.
In most of the designs, if the max path (setup) requires N clock cycles, it is not feasible to achieve the min path constraint to be greater than (N-1) clock cycles.

It is possible that certain timing paths are not real (or not possible) in the actual functional operation of the design.
Such paths can be turned off during STA by setting these as false paths.
Examples of false paths are
- Clock pin of a flip-flop to input of another flip-flop
- Through pins of multiple cells
Too many false paths which are wildcarded using through specification can slow down the analysis

set_false_path -through [get_pins UMX]
The -through option adds run time complexity.

If a design has both negative-triggered and positive-triggered flip-flops, then it it like that half-cycle paths exists in the design.

It ensures that there is adequate time between an active clock edge and the release of an asynchronous control signal.
Asynchronous control signal is released well after the active clock edge so that the clock edge can have no effect.

This ensures that there is minimum amount of time between the asynchronous signal becoming inactive and the next active clock edge.
This check ensures that after the asynchronous signal becomes inactive, there is adequate time to recover so that the next active clock edge can be effective.