Sanity Checks

• Following are the sanity checks performed before implementing the Physical Design flow

  • Library check
  • Netlist Check
  • SDC Check

Library check

• It performs a consistency check between logical library (.lib) and physical libraries (.lef).

• If any particular cell used in the design does not have LEF view or missing any timing/ power/ logic information then we can resolve the issue in the initial stage.

  • Innovus Commands

    1. checkDesign -timingLibrary
    2. checkDesign -physicalLibrary
    3. checkDesign -all

  • ICC2 commands

    1. check_library

Netlist check

• Innovus command

  • checkDesign -netlist

• ICC2

  • check_design

• Following are the possible netlist checks

  • Floating input pins and nets
  • No direct connection between VDD and VSS
  • Multidriven nets
  • Combinational loops
  • Unloaded outputs
  • Unconstrained pins
  • Mismatch pin count between instance and reference

SDC check

• Unconstrained path
• Clock is reaching to all synchronous elements
• Multi driven registers
• Unconstrained endpoint
• I/O delay missing for a port
• Slew or load constraint missing for a port
• Missing clock definition

Innovus and ICC2 command

• check_timning